diff --git a/fsi_master.v b/fsi_master.v
index 753d940cd96fb1decf6af3e2a854adca8ac4d22c..d2f1da93c68784fd4e395aa9627e4669ed2fd2a5 100644
--- a/fsi_master.v
+++ b/fsi_master.v
@@ -10,6 +10,7 @@ module fsi_master_interface(
 		output reg [31:0] rx_data,
 		input wire [1:0] data_length,			// 0 == 8 bit, 1 == 16 bit, 2 = 32 bit (NOTE: the lower two address bits may be forced if 16 bit / 32 bit transfer length is set)
 		input wire data_direction,			// 0 == read from slave, 1 == write to slave
+		input wire enable_relative_address,
 		input wire start_cycle,
 		output wire cycle_complete,
 		output wire [2:0] cycle_error,
@@ -124,6 +125,7 @@ module fsi_master_interface(
 	reg [20:0] address_tx_reg = 0;
 	reg [31:0] tx_data_reg = 0;
 	reg [31:0] rx_data_reg = 0;
+	reg enable_relative_address_reg = 0;
 	reg [1:0] enhanced_error_recovery_reg = 0;
 	reg [8:0] cycle_counter = 0;
 	reg [20:0] last_address = 0;
@@ -226,6 +228,7 @@ module fsi_master_interface(
 							default: address_reg <= address[20:0];
 						endcase
 						tx_data_reg <= tx_data;
+						enable_relative_address_reg <= enable_relative_address;
 						enhanced_error_recovery_reg <= enhanced_error_recovery;
 						slave_error_recovery_state <= 0;
 						master_error_recovery_state <= 0;
@@ -284,21 +287,27 @@ module fsi_master_interface(
 					crc_protected_bits_transmitting = 1;
 					fsi_data_reg_internal = slave_id_reg[0];
 					if (!fsi_command_code_set) begin
-						if (last_address_valid && (last_address[20:2] == address_reg[20:2])) begin
-							fsi_command_code <= FSI_CODEWORD_TX_MSG_SAME_ADR_DAT;
-							fsi_command_code_length <= FSI_CODEWORD_TX_MSG_SAME_ADR_LEN;
-							cycle_counter <= FSI_CODEWORD_TX_MSG_SAME_ADR_LEN;
-						end else if (last_address_valid && (last_address[20:8] == address_reg[20:8])) begin
-							fsi_command_code <= FSI_CODEWORD_TX_MSG_REL_ADR_DAT;
-							fsi_command_code_length <= FSI_CODEWORD_TX_MSG_REL_ADR_LEN;
-							cycle_counter <= FSI_CODEWORD_TX_MSG_REL_ADR_LEN;
-							if (address_reg < last_address) begin
-								fsi_rel_address_delta_negative <= 1;
+						if (enable_relative_address_reg) begin
+							if (last_address_valid && (last_address[20:2] == address_reg[20:2])) begin
+								fsi_command_code <= FSI_CODEWORD_TX_MSG_SAME_ADR_DAT;
+								fsi_command_code_length <= FSI_CODEWORD_TX_MSG_SAME_ADR_LEN;
+								cycle_counter <= FSI_CODEWORD_TX_MSG_SAME_ADR_LEN;
+							end else if (last_address_valid && (last_address[20:8] == address_reg[20:8])) begin
+								fsi_command_code <= FSI_CODEWORD_TX_MSG_REL_ADR_DAT;
+								fsi_command_code_length <= FSI_CODEWORD_TX_MSG_REL_ADR_LEN;
+								cycle_counter <= FSI_CODEWORD_TX_MSG_REL_ADR_LEN;
+								if (address_reg < last_address) begin
+									fsi_rel_address_delta_negative <= 1;
+								end else begin
+									fsi_rel_address_delta_negative <= 0;
+								end
+								// Relative delta is actually 9-bit two's complement, but fsi_rel_address_delta_negative is used as bit 8
+								fsi_rel_address_delta = address_reg - last_address;
 							end else begin
-								fsi_rel_address_delta_negative <= 0;
+								fsi_command_code <= FSI_CODEWORD_TX_MSG_ABS_ADR_DAT;
+								fsi_command_code_length <= FSI_CODEWORD_TX_MSG_ABS_ADR_LEN;
+								cycle_counter <= FSI_CODEWORD_TX_MSG_ABS_ADR_LEN;
 							end
-							// Relative delta is actually 9-bit two's complement, but fsi_rel_address_delta_negative is used as bit 8
-							fsi_rel_address_delta = address_reg - last_address;
 						end else begin
 							fsi_command_code <= FSI_CODEWORD_TX_MSG_ABS_ADR_DAT;
 							fsi_command_code_length <= FSI_CODEWORD_TX_MSG_ABS_ADR_LEN;