Fix I_POLL_RSP receiver logic and expose interrupt / DMA fields on external interface

fsi_master.v

@@ -16,6 +16,8 @@ module fsi_master_interface(
 		input wire [1:0] enhanced_error_recovery,	// Bit 1 == EER for IPOLL, Bit 0 == EER for all other transmissions
 		input wire enable_ipoll,
 		output wire ipoll_error,
+		output wire [1:0] interrupt_field,
+		output wire [2:0] dma_control_field,
 
 		output wire fsi_data_out,			// Must have I/O output register enabled in top level SB_IO or equivalent, output data driven at falling edge of clock
 		input wire fsi_data_in,
@@ -100,6 +102,8 @@ module fsi_master_interface(
 	reg cycle_complete_reg = 0;
 	reg [2:0] cycle_error_reg = 0;
 	reg ipoll_error_reg = 0;
+	reg [1:0] interrupt_field_reg = 0;
+	reg [2:0] dma_control_field_reg = 0;
 	assign fsi_clock_out = peripheral_clock;	// Clock is allowed to always run
 	assign fsi_data_out = ~fsi_data_reg;		// FSI data line is electrically inverted
 	assign fsi_data_in_internal = ~fsi_data_in;
@@ -107,6 +111,8 @@ module fsi_master_interface(
 	assign cycle_complete = cycle_complete_reg;
 	assign cycle_error = cycle_error_reg;
 	assign ipoll_error = ipoll_error_reg;
+	assign interrupt_field = interrupt_field_reg;
+	assign dma_control_field = dma_control_field_reg;
 
 	// Low level protocol handler
 	reg start_cycle_prev = 0;
@@ -131,8 +137,6 @@ module fsi_master_interface(
 	reg crc_feedback = 0;
 	reg [7:0] control_state = 0;
 	reg [1:0] rx_slave_id = 0;
-	reg [1:0] interrupt_field = 0;
-	reg [2:0] dma_control_field = 0;
 	reg [1:0] rx_message_type = 0;
 	reg [8:0] timeout_counter = 0;
 	reg fsi_rel_address_delta_negative = 0;
@@ -144,6 +148,8 @@ module fsi_master_interface(
 	reg [7:0] ipoll_start_timer = 0;
 	reg ipoll_in_process = 0;
 	reg [1:0] commands_since_last_ipoll = 0;
+	reg [1:0] interrupt_field_internal = 0;
+	reg [2:0] dma_control_field_internal = 0;
 	always @(posedge peripheral_clock) begin
 		if (peripheral_reset) begin
 			cycle_complete_reg <= 0;
@@ -615,6 +621,10 @@ module fsi_master_interface(
 							crc_data <= 0;
 							control_state <= FSI_TRANSFER_STATE_TX11;
 						end else begin
+							if (ipoll_in_process) begin
+								interrupt_field_reg <= interrupt_field_internal;
+								dma_control_field_reg <= dma_control_field_internal;
+							end
 							master_error_recovery_state <= 0;
 							control_state <= FSI_TRANSFER_STATE_TR01;
 						end
@@ -707,31 +717,31 @@ module fsi_master_interface(
 				FSI_TRANSFER_STATE_IR01: begin
 					// Receive interrupt field, bit 1
 					crc_protected_bits_receiving = 1;
-					interrupt_field[1] <= fsi_data_in_internal;
+					interrupt_field_internal[1] <= fsi_data_in_internal;
 					control_state <= FSI_TRANSFER_STATE_IR02;
 				end
 				FSI_TRANSFER_STATE_IR02: begin
 					// Receive interrupt field, bit 2
 					crc_protected_bits_receiving = 1;
-					interrupt_field[0] <= fsi_data_in_internal;
+					interrupt_field_internal[0] <= fsi_data_in_internal;
 					control_state <= FSI_TRANSFER_STATE_IR03;
 				end
 				FSI_TRANSFER_STATE_IR03: begin
 					// Receive DMA control field, bit 1
 					crc_protected_bits_receiving = 1;
-					dma_control_field[2] <= fsi_data_in_internal;
+					dma_control_field_internal[2] <= fsi_data_in_internal;
 					control_state <= FSI_TRANSFER_STATE_IR04;
 				end
 				FSI_TRANSFER_STATE_IR04: begin
 					// Receive DMA control field, bit 2
 					crc_protected_bits_receiving = 1;
-					dma_control_field[1] <= fsi_data_in_internal;
+					dma_control_field_internal[1] <= fsi_data_in_internal;
 					control_state <= FSI_TRANSFER_STATE_IR05;
 				end
 				FSI_TRANSFER_STATE_IR05: begin
 					// Receive DMA control field, bit 3
 					crc_protected_bits_receiving = 1;
-					dma_control_field[0] <= fsi_data_in_internal;
+					dma_control_field_internal[0] <= fsi_data_in_internal;
 					cycle_counter <= 4;
 					control_state <= FSI_TRANSFER_STATE_RX06;
 				end