Shave a master clock cycle off the SPI transfer by initiating frame start on...

Shave a master clock cycle off the SPI transfer by initiating frame start on transition from idle state
parent 7a3bacb9
...@@ -48,8 +48,14 @@ module spi_master_interface( ...@@ -48,8 +48,14 @@ module spi_master_interface(
transaction_complete <= 0; transaction_complete <= 0;
state_iteration <= 0; state_iteration <= 0;
if (cycle_start_reg) begin if (cycle_start_reg) begin
// Set up transfer
rx_data <= 0; rx_data <= 0;
data_shift_out <= tx_data_reg; data_shift_out <= tx_data_reg;
// Drive frame start
spi_clock <= 1'b1;
spi_ss_n <= 1'b0;
transfer_state <= 1; transfer_state <= 1;
end else begin end else begin
if (!hold_ss_active_reg) begin if (!hold_ss_active_reg) begin
...@@ -59,21 +65,14 @@ module spi_master_interface( ...@@ -59,21 +65,14 @@ module spi_master_interface(
end end
end end
1: begin 1: begin
// Drive frame start
spi_clock <= 1'b1;
spi_ss_n <= 1'b0;
state_iteration <= 0;
transfer_state <= 2;
end
2: begin
// Shift out TX byte / toggle clock // Shift out TX byte / toggle clock
spi_clock <= 1'b0; spi_clock <= 1'b0;
spi_ss_n <= 1'b0; spi_ss_n <= 1'b0;
spi_mosi <= data_shift_out[7]; spi_mosi <= data_shift_out[7];
data_shift_out <= data_shift_out << 1; data_shift_out <= data_shift_out << 1;
transfer_state <= 3; transfer_state <= 2;
end end
3: begin 2: begin
// Shift in RX byte / toggle clock // Shift in RX byte / toggle clock
spi_clock <= 1'b1; spi_clock <= 1'b1;
spi_ss_n <= 1'b0; spi_ss_n <= 1'b0;
...@@ -86,12 +85,12 @@ module spi_master_interface( ...@@ -86,12 +85,12 @@ module spi_master_interface(
ss_state_at_idle <= 1'b1; ss_state_at_idle <= 1'b1;
end end
transaction_complete <= 1; transaction_complete <= 1;
transfer_state <= 4; transfer_state <= 3;
end else begin end else begin
transfer_state <= 2; transfer_state <= 1;
end end
end end
4: begin 3: begin
// Wait for host to deassert transaction request // Wait for host to deassert transaction request
if (!cycle_start_reg) begin if (!cycle_start_reg) begin
transaction_complete <= 0; transaction_complete <= 0;
......
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