Clarify FSI electrical protocol requirements based on analyzed operation of IBM POWER9 hardware

parent 2fcce36b
...@@ -19,10 +19,10 @@ module fsi_master_interface( ...@@ -19,10 +19,10 @@ module fsi_master_interface(
output wire [1:0] interrupt_field, output wire [1:0] interrupt_field,
output wire [2:0] dma_control_field, output wire [2:0] dma_control_field,
output wire fsi_data_out, // Must have I/O output register enabled in top level SB_IO or equivalent, output data driven at falling edge of clock output wire fsi_data_out, // Must have I/O output register enabled in top level SB_IO or equivalent, output data driven at rising edge of clock
input wire fsi_data_in, input wire fsi_data_in,
output wire fsi_data_direction, // 0 == tristate (input), 1 == driven (output) output wire fsi_data_direction, // 0 == tristate (input), 1 == driven (output)
output wire fsi_clock_out, output wire fsi_clock_out, // Must be inverted at the edge driver -- rising clocks are in reference to this signal, not the electrically inverted signal on the FSI bus
output wire [7:0] debug_port, output wire [7:0] debug_port,
......
...@@ -16,10 +16,10 @@ module fsi_slave_interface( ...@@ -16,10 +16,10 @@ module fsi_slave_interface(
input wire [1:0] interrupt_field, input wire [1:0] interrupt_field,
input wire [2:0] dma_control_field, input wire [2:0] dma_control_field,
output wire fsi_data_out, // Must have I/O output register enabled in top level SB_IO or equivalent, output data driven at falling edge of clock output wire fsi_data_out, // Must have I/O output register enabled in top level SB_IO or equivalent, output data driven at rising edge of clock
input wire fsi_data_in, input wire fsi_data_in,
output wire fsi_data_direction, // 0 == tristate (input), 1 == driven (output) output wire fsi_data_direction, // 0 == tristate (input), 1 == driven (output)
input wire fsi_clock_in, input wire fsi_clock_in, // Must not be inverted by the edge latch
output wire [7:0] debug_port, output wire [7:0] debug_port,
......
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