diff --git a/fsi_master.v b/fsi_master.v
index 91352912d4a4c0cf5e9c20ad844bf21496b50aa6..4ee793a39031effffec3f1e5cb520850cc6d1453 100644
--- a/fsi_master.v
+++ b/fsi_master.v
@@ -19,10 +19,10 @@ module fsi_master_interface(
 		output wire [1:0] interrupt_field,
 		output wire [2:0] dma_control_field,
 
-		output wire fsi_data_out,			// Must have I/O output register enabled in top level SB_IO or equivalent, output data driven at falling edge of clock
+		output wire fsi_data_out,			// Must have I/O output register enabled in top level SB_IO or equivalent, output data driven at rising edge of clock
 		input wire fsi_data_in,
 		output wire fsi_data_direction,			// 0 == tristate (input), 1 == driven (output)
-		output wire fsi_clock_out,
+		output wire fsi_clock_out,			// Must be inverted at the edge driver -- rising clocks are in reference to this signal, not the electrically inverted signal on the FSI bus
 
 		output wire [7:0] debug_port,
 
diff --git a/fsi_slave.v b/fsi_slave.v
index f7058765d8baa9dbae3541f562a70b3cffb23c69..b46af0ea9a5e3b94a27bd61bdc82233d016b2511 100644
--- a/fsi_slave.v
+++ b/fsi_slave.v
@@ -16,10 +16,10 @@ module fsi_slave_interface(
 		input wire [1:0] interrupt_field,
 		input wire [2:0] dma_control_field,
 
-		output wire fsi_data_out,			// Must have I/O output register enabled in top level SB_IO or equivalent, output data driven at falling edge of clock
+		output wire fsi_data_out,			// Must have I/O output register enabled in top level SB_IO or equivalent, output data driven at rising edge of clock
 		input wire fsi_data_in,
 		output wire fsi_data_direction,			// 0 == tristate (input), 1 == driven (output)
-		input wire fsi_clock_in,
+		input wire fsi_clock_in,			// Must not be inverted by the edge latch
 
 		output wire [7:0] debug_port,