Fix passage of received data from FSI master to higher logic levels

parent 7a6a81e7
...@@ -158,6 +158,7 @@ module fsi_master_interface( ...@@ -158,6 +158,7 @@ module fsi_master_interface(
always @(posedge peripheral_clock) begin always @(posedge peripheral_clock) begin
if (peripheral_reset) begin if (peripheral_reset) begin
cycle_complete_reg <= 0; cycle_complete_reg <= 0;
rx_data <= 0;
last_address_valid <= 0; last_address_valid <= 0;
ipoll_in_process <= 0; ipoll_in_process <= 0;
busy_response_in_process <= 0; busy_response_in_process <= 0;
...@@ -719,6 +720,7 @@ module fsi_master_interface( ...@@ -719,6 +720,7 @@ module fsi_master_interface(
end else begin end else begin
// Transfer complete! // Transfer complete!
if (!ipoll_in_process) begin if (!ipoll_in_process) begin
rx_data <= rx_data_reg;
cycle_complete_reg <= 1; cycle_complete_reg <= 1;
end end
busy_response_in_process <= 0; busy_response_in_process <= 0;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment