From 4b521c9a0f92fc3827e87a1c476426c9c723287f Mon Sep 17 00:00:00 2001 From: Raptor Engineering Development Team Date: Mon, 8 Jun 2020 02:37:06 -0500 Subject: [PATCH] Fix passage of received data from FSI master to higher logic levels --- fsi_master.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fsi_master.v b/fsi_master.v index 66defef..196ca4f 100644 --- a/fsi_master.v +++ b/fsi_master.v @@ -158,6 +158,7 @@ module fsi_master_interface( always @(posedge peripheral_clock) begin if (peripheral_reset) begin cycle_complete_reg <= 0; + rx_data <= 0; last_address_valid <= 0; ipoll_in_process <= 0; busy_response_in_process <= 0; @@ -719,6 +720,7 @@ module fsi_master_interface( end else begin // Transfer complete! if (!ipoll_in_process) begin + rx_data <= rx_data_reg; cycle_complete_reg <= 1; end busy_response_in_process <= 0; -- 2.30.2