Add word transfer mode to SPI core in quad SPI mode

Switch main sequencer to use word transfer for firmware reads.
parent 3dd9d47e
This diff is collapsed.
...@@ -125,11 +125,12 @@ endmodule ...@@ -125,11 +125,12 @@ endmodule
module spi_master_interface_quad( module spi_master_interface_quad(
input wire platform_clock, input wire platform_clock,
input wire reset, input wire reset,
input wire [7:0] tx_data, input wire [31:0] tx_data,
output reg [7:0] rx_data, output reg [31:0] rx_data,
input wire [7:0] dummy_cycle_count, input wire [7:0] dummy_cycle_count,
input wire hold_ss_active, input wire hold_ss_active,
input wire qspi_mode_active, input wire qspi_mode_active,
input wire qspi_transfer_mode, // 0 == byte transfer, 1 == word transfer
input wire qspi_transfer_direction, // 0 == read (input), 1 == write (output) input wire qspi_transfer_direction, // 0 == read (input), 1 == write (output)
input wire cycle_start, input wire cycle_start,
output reg transaction_complete, output reg transaction_complete,
...@@ -149,7 +150,7 @@ module spi_master_interface_quad( ...@@ -149,7 +150,7 @@ module spi_master_interface_quad(
); );
reg [3:0] transfer_state = 0; reg [3:0] transfer_state = 0;
reg [7:0] data_shift_out = 0; reg [31:0] data_shift_out = 0;
reg [7:0] state_iteration = 0; reg [7:0] state_iteration = 0;
reg ss_state_at_idle = 1'b1; reg ss_state_at_idle = 1'b1;
...@@ -157,6 +158,9 @@ module spi_master_interface_quad( ...@@ -157,6 +158,9 @@ module spi_master_interface_quad(
reg [7:0] dummy_cycle_count_reg = 0; reg [7:0] dummy_cycle_count_reg = 0;
reg [7:0] dummy_cycle_ctr = 0; reg [7:0] dummy_cycle_ctr = 0;
reg qspi_transfer_mode_reg = 0;
reg [3:0] qspi_transfer_cycle_stop_value = 1;
always @(posedge platform_clock) begin always @(posedge platform_clock) begin
if (reset) begin if (reset) begin
transfer_state <= 0; transfer_state <= 0;
...@@ -188,6 +192,14 @@ module spi_master_interface_quad( ...@@ -188,6 +192,14 @@ module spi_master_interface_quad(
data_shift_out <= tx_data; data_shift_out <= tx_data;
spi_quad_mode_pin_enable <= qspi_mode_active; spi_quad_mode_pin_enable <= qspi_mode_active;
spi_data_direction <= qspi_transfer_direction; spi_data_direction <= qspi_transfer_direction;
qspi_transfer_mode_reg <= qspi_transfer_mode;
if (qspi_transfer_mode == 0) begin
// Byte transfer (2 nibbles per word)
qspi_transfer_cycle_stop_value <= 1;
end else begin
// Word transfer (4 bytes / 8 nibbles per word)
qspi_transfer_cycle_stop_value <= 7;
end
// Drive frame start // Drive frame start
spi_clock <= 1'b1; spi_clock <= 1'b1;
...@@ -207,10 +219,17 @@ module spi_master_interface_quad( ...@@ -207,10 +219,17 @@ module spi_master_interface_quad(
spi_clock <= 1'b0; spi_clock <= 1'b0;
spi_ss_n <= 1'b0; spi_ss_n <= 1'b0;
if (spi_quad_mode_pin_enable) begin if (spi_quad_mode_pin_enable) begin
spi_d3_out <= data_shift_out[7]; if (qspi_transfer_mode_reg) begin
spi_d2_out <= data_shift_out[6]; spi_d3_out <= data_shift_out[31];
spi_d1_out <= data_shift_out[5]; spi_d2_out <= data_shift_out[30];
spi_d0_out <= data_shift_out[4]; spi_d1_out <= data_shift_out[29];
spi_d0_out <= data_shift_out[28];
end else begin
spi_d3_out <= data_shift_out[7];
spi_d2_out <= data_shift_out[6];
spi_d1_out <= data_shift_out[5];
spi_d0_out <= data_shift_out[4];
end
data_shift_out <= data_shift_out << 4; data_shift_out <= data_shift_out << 4;
end else begin end else begin
spi_d0_out <= data_shift_out[7]; spi_d0_out <= data_shift_out[7];
...@@ -224,8 +243,12 @@ module spi_master_interface_quad( ...@@ -224,8 +243,12 @@ module spi_master_interface_quad(
spi_ss_n <= 1'b0; spi_ss_n <= 1'b0;
state_iteration <= state_iteration + 1; state_iteration <= state_iteration + 1;
if (spi_quad_mode_pin_enable) begin if (spi_quad_mode_pin_enable) begin
rx_data <= {rx_data[3:0], spi_d3_in, spi_d2_in, spi_d1_in, spi_d0_in}; if (qspi_transfer_mode_reg) begin
if (state_iteration >= 1) begin rx_data <= {rx_data[27:0], spi_d3_in, spi_d2_in, spi_d1_in, spi_d0_in};
end else begin
rx_data <= {rx_data[3:0], spi_d3_in, spi_d2_in, spi_d1_in, spi_d0_in};
end
if (state_iteration >= qspi_transfer_cycle_stop_value) begin
if (hold_ss_active) begin if (hold_ss_active) begin
ss_state_at_idle <= 1'b0; ss_state_at_idle <= 1'b0;
end else begin end else begin
......
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