clock_generator.v 2.22 KB
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// © 2017 - 2020 Raptor Engineering, LLC
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//
// Released under the terms of the AGPL v3
// See the LICENSE file for full details

// `define SIMULATION 1

// Because timing constraints are not yet implemented in arachne-pnr,
// it can be difficult to ensure a high enough implemented frequency
// for proper CPU operation.  Allow slowing of the main CPU clock by
// around 5% to 22.875MHz if needed
// `define USE_22_875MHZ_CLOCK 1

module clock_generator(
		// Main 12MHz platform clock
		input wire platform_clock,
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		output wire spi_core_pll_lock,
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		output wire slow_1843khz_uart_clock,
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		output wire slow_175khz_platform_clock,
		output wire slow_183hz_platform_clock,
		output wire slow_11hz_platform_clock,

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		// Main 33MHz LPC clock
		input wire lpc_clock,
		output wire sequencer_clock,
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		output wire spi_core_clock,
		input wire reset_lpc_derived_plls
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	);

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`ifdef SIMULATION
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	assign spi_core_clock = lpc_clock;
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`else
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	// 66MHz SPI core clock
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	SB_PLL40_CORE #(
		.FEEDBACK_PATH("SIMPLE"),
		.PLLOUT_SELECT("GENCLK"),
		.DIVR(4'b0000),
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		.DIVF(7'b0001111),
		.DIVQ(3'b011),
		.FILTER_RANGE(3'b011)
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	) platform_pll (
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		.LOCK(spi_core_pll_lock),
		.RESETB(~reset_lpc_derived_plls),
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		.BYPASS(1'b0),
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		.REFERENCECLK(lpc_clock),
		.PLLOUTGLOBAL(spi_core_clock)
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	);
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`endif
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	// UART clock generator
	reg internal_1843khz_clock;
	reg [5:0] uart_clock_counter = 0;
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	always @(posedge lpc_clock) begin
		if (uart_clock_counter < 8) begin
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			uart_clock_counter <= uart_clock_counter + 1;
		end else begin
			internal_1843khz_clock <= ~internal_1843khz_clock;
			uart_clock_counter <= 0;
		end
	end

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	// Slow clock generator
	reg [20:0] slow_clock_counter = 0;
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	always @(posedge platform_clock) begin
		slow_clock_counter = slow_clock_counter + 4;
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	end

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	// Buffer 1843Hz slow clock
	SB_GB platform_1843khz_clock_buffer (
		.USER_SIGNAL_TO_GLOBAL_BUFFER(internal_1843khz_clock),
		.GLOBAL_BUFFER_OUTPUT(slow_1843khz_uart_clock)
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	);

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	// 175KHz slow clock
	assign slow_175khz_platform_clock = slow_clock_counter[5];

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	// 183.10546875Hz slow clock
	assign slow_183hz_platform_clock = slow_clock_counter[16];

	// 11.44091796875Hz slow clock
	assign slow_11hz_platform_clock = slow_clock_counter[20];
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	// Generate sequencer clock
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	assign sequencer_clock = lpc_clock;
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endmodule