fsi_master.v 32.7 KB
Newer Older
1 2 3 4 5 6 7 8 9 10
// © 2020 Raptor Engineering, LLC
//
// Released under the terms of the AGPL v3
// See the LICENSE file for full details

module fsi_master_interface(
		input wire [1:0] slave_id,
		input wire [20:0] address,
		input wire [31:0] tx_data,
		output reg [31:0] rx_data,
11
		input wire [1:0] data_length,			// 0 == 8 bit, 1 == 16 bit, 2 = 32 bit (NOTE: the lower two address bits may be forced if 16 bit / 32 bit transfer length is set)
12
		input wire data_direction,			// 0 == read from slave, 1 == write to slave
13
		input wire enable_relative_address,
14
		input wire enable_extended_address_mode,	// In 23-bit extended address mode, the complete address is {slave_id, address}
15
		input wire enable_crc_protection,
16 17 18 19
		input wire start_cycle,
		output wire cycle_complete,
		output wire [2:0] cycle_error,
		input wire [1:0] enhanced_error_recovery,	// Bit 1 == EER for IPOLL, Bit 0 == EER for all other transmissions
20
		input wire [7:0] internal_cmd_issue_delay,
21 22
		input wire enable_ipoll,
		output wire ipoll_error,
23 24
		output wire [1:0] interrupt_field,
		output wire [2:0] dma_control_field,
25

26
		output wire fsi_data_out,			// Must have I/O output register enabled in top level SB_IO or equivalent, output data driven at rising edge of clock
27
		input wire fsi_data_in,
28
		output wire fsi_data_direction,			// 0 == tristate (input), 1 == driven (output)
29
		output wire fsi_clock_out,			// Must be inverted at the edge driver -- rising clocks are in reference to this signal, not the electrically inverted signal on the FSI bus
30

31 32
		output wire [7:0] debug_port,

33 34 35 36 37
		input wire peripheral_reset,
		input wire peripheral_clock
	);

	parameter FSI_TIMEOUT_CYCLES = 256;
38
	parameter FSI_TURNAROUND_CYCLES = 3;
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
	parameter FSI_MASTER_TIMEOUT_CYCLES = 166000;	// Assumes 166MHz clock, 1ms timeout
	parameter FSI_IPOLL_IDLE_START_CYCLES = 128;	// This fires every ~786ns during idle periods if a 166MHz clock is used
	parameter FSI_IPOLL_MAX_SEQ_STD_COMMANDS = 2;	// Two commands can fire back-to-back without an IPOLL before an IPOLL is forcibly inserted

	// Command codes are variable length
	parameter FSI_CODEWORD_TX_MSG_BREAK_LEN = 256;
	parameter FSI_CODEWORD_TX_MSG_ABS_ADR_DAT = 3'b100;
	parameter FSI_CODEWORD_TX_MSG_ABS_ADR_LEN = 3;
	parameter FSI_CODEWORD_TX_MSG_REL_ADR_DAT = 3'b101;
	parameter FSI_CODEWORD_TX_MSG_REL_ADR_LEN = 3;
	parameter FSI_CODEWORD_TX_MSG_SAME_ADR_DAT = 2'b11;
	parameter FSI_CODEWORD_TX_MSG_SAME_ADR_LEN = 2;
	parameter FSI_CODEWORD_TX_MSG_D_POLL_DAT = 3'b010;
	parameter FSI_CODEWORD_TX_MSG_D_POLL_LEN = 3;
	parameter FSI_CODEWORD_TX_MSG_E_POLL_DAT = 3'b011;
	parameter FSI_CODEWORD_TX_MSG_E_POLL_LEN = 3;
	parameter FSI_CODEWORD_TX_MSG_I_POLL_DAT = 3'b001;
	parameter FSI_CODEWORD_TX_MSG_I_POLL_LEN = 3;
	parameter FSI_CODEWORD_TX_MSG_TERM_DAT = 6'b111111;
	parameter FSI_CODEWORD_TX_MSG_TERM_LEN = 6;

	// All response codes are 2 bits long
	parameter FSI_CODEWORD_RX_MSG_ACK = 2'b00;
	parameter FSI_CODEWORD_RX_MSG_BUSY = 2'b01;
	parameter FSI_CODEWORD_RX_MSG_ERR_A = 2'b10;
	parameter FSI_CODEWORD_RX_MSG_ERR_C = 2'b11;

	parameter FSI_ERROR_NONE = 0;
	parameter FSI_ERROR_TIMEOUT = 1;
	parameter FSI_ERROR_MASTER_TIMEOUT = 2;
	parameter FSI_ERROR_INVALID_CODEWORD = 3;
	parameter FSI_ERROR_BAD_TX_CHECKSUM = 4;
	parameter FSI_ERROR_BAD_RX_CHECKSUM = 5;
	parameter FSI_ERROR_INTERNAL_FAULT = 6;

	parameter FSI_INITIALIZE_STATE_01 = 0;
	parameter FSI_INITIALIZE_STATE_02 = 1;
	parameter FSI_INITIALIZE_STATE_03 = 2;
77 78 79 80 81 82 83 84 85 86 87 88
	parameter FSI_TRANSFER_STATE_IDLE = 16;
	parameter FSI_TRANSFER_STATE_TX01 = 17;
	parameter FSI_TRANSFER_STATE_TX02 = 18;
	parameter FSI_TRANSFER_STATE_TX03 = 19;
	parameter FSI_TRANSFER_STATE_TX04 = 20;
	parameter FSI_TRANSFER_STATE_TX05 = 21;
	parameter FSI_TRANSFER_STATE_TX06 = 22;
	parameter FSI_TRANSFER_STATE_TX07 = 23;
	parameter FSI_TRANSFER_STATE_TX08 = 24;
	parameter FSI_TRANSFER_STATE_TX09 = 25;
	parameter FSI_TRANSFER_STATE_TX10 = 26;
	parameter FSI_TRANSFER_STATE_TX11 = 27;
89 90 91 92 93 94 95 96 97 98 99 100 101 102 103
	parameter FSI_TRANSFER_STATE_RX01 = 32;
	parameter FSI_TRANSFER_STATE_RX02 = 33;
	parameter FSI_TRANSFER_STATE_RX03 = 34;
	parameter FSI_TRANSFER_STATE_RX04 = 35;
	parameter FSI_TRANSFER_STATE_RX05 = 36;
	parameter FSI_TRANSFER_STATE_RX06 = 37;
	parameter FSI_TRANSFER_STATE_RX07 = 38;
	parameter FSI_TRANSFER_STATE_RX08 = 39;
	parameter FSI_TRANSFER_STATE_IR01 = 48;
	parameter FSI_TRANSFER_STATE_IR02 = 49;
	parameter FSI_TRANSFER_STATE_IR03 = 50;
	parameter FSI_TRANSFER_STATE_IR04 = 51;
	parameter FSI_TRANSFER_STATE_IR05 = 52;
	parameter FSI_TRANSFER_STATE_TR01 = 64;
	parameter FSI_TRANSFER_STATE_TR02 = 65;
104
	parameter FSI_TRANSFER_STATE_DL01 = 96;
105 106 107 108 109 110 111

	reg fsi_data_reg = 0;
	wire fsi_data_in_internal;
	reg fsi_data_direction_reg = 0;
	reg cycle_complete_reg = 0;
	reg [2:0] cycle_error_reg = 0;
	reg ipoll_error_reg = 0;
112 113
	reg [1:0] interrupt_field_reg = 0;
	reg [2:0] dma_control_field_reg = 0;
114 115
	assign fsi_clock_out = peripheral_clock;	// Clock is allowed to always run
	assign fsi_data_out = ~fsi_data_reg;		// FSI data line is electrically inverted
116
	assign fsi_data_in_internal = ~fsi_data_in;
117 118 119 120
	assign fsi_data_direction = fsi_data_direction_reg;
	assign cycle_complete = cycle_complete_reg;
	assign cycle_error = cycle_error_reg;
	assign ipoll_error = ipoll_error_reg;
121 122
	assign interrupt_field = interrupt_field_reg;
	assign dma_control_field = dma_control_field_reg;
123 124 125 126 127 128 129 130 131

	// Low level protocol handler
	reg data_direction_reg = 0;
	reg [1:0] data_length_reg = 0;
	reg [1:0] slave_id_reg = 0;
	reg [20:0] address_reg = 0;
	reg [20:0] address_tx_reg = 0;
	reg [31:0] tx_data_reg = 0;
	reg [31:0] rx_data_reg = 0;
132
	reg enable_relative_address_reg = 0;
133
	reg enable_extended_address_mode_reg = 0;
134
	reg enable_crc_protection_reg = 0;
135
	reg [1:0] enhanced_error_recovery_reg = 0;
136
	reg [7:0] internal_cmd_issue_delay_reg = 0;
137
	reg [8:0] cycle_counter = 0;
138
	reg [7:0] delay_counter = 0;
139 140 141
	reg [20:0] last_address = 0;
	reg last_address_valid = 0;
	reg [7:0] fsi_command_code = 0;
142
	reg [7:0] fsi_command_code_length = 0;
143 144 145 146 147 148 149
	reg fsi_command_code_set = 0;
	reg crc_protected_bits_transmitting = 0;
	reg crc_protected_bits_receiving = 0;
	reg fsi_data_reg_internal = 0;
	reg [3:0] crc_data = 0;
	reg crc_feedback = 0;
	reg [7:0] control_state = 0;
150
	reg [7:0] post_delay_control_state = 0;
151 152 153 154 155 156 157 158 159 160 161
	reg [1:0] rx_slave_id = 0;
	reg [1:0] rx_message_type = 0;
	reg [8:0] timeout_counter = 0;
	reg fsi_rel_address_delta_negative = 0;
	reg [7:0] fsi_rel_address_delta = 0;
	reg fsi_master_timeout_counting = 0;
	reg [23:0] fsi_master_timeout_counter = 0;
	reg [1:0] slave_error_recovery_state = 0;
	reg [1:0] master_error_recovery_state = 0;
	reg [7:0] ipoll_start_timer = 0;
	reg ipoll_in_process = 0;
162
	reg busy_response_in_process = 0;
163
	reg [1:0] commands_since_last_ipoll = 0;
164 165
	reg [1:0] interrupt_field_internal = 0;
	reg [2:0] dma_control_field_internal = 0;
166 167 168

	assign debug_port = control_state;

169 170 171
	always @(posedge peripheral_clock) begin
		if (peripheral_reset) begin
			cycle_complete_reg <= 0;
172
			rx_data <= 0;
173
			last_address_valid <= 0;
174 175
			ipoll_in_process <= 0;
			busy_response_in_process <= 0;
176 177 178 179
			control_state <= FSI_INITIALIZE_STATE_01;
		end else begin
			case (control_state)
				FSI_INITIALIZE_STATE_01: begin
180 181 182 183
					// Global (re)-initialization
					ipoll_in_process <= 0;
					busy_response_in_process <= 0;

184
					// Set up BREAK command
185
					cycle_counter <= FSI_CODEWORD_TX_MSG_BREAK_LEN;
186 187 188 189
					control_state <= FSI_INITIALIZE_STATE_02;
				end
				FSI_INITIALIZE_STATE_02: begin
					// Send BREAK command
190
					// BREAK is *not* CRC protected!
191 192
					if (cycle_counter > 0) begin
						fsi_data_direction_reg <= 1;
193 194
						crc_protected_bits_transmitting = 0;
						crc_protected_bits_receiving = 0;
195 196
						fsi_data_reg_internal = 1;
						if (cycle_counter == 1) begin
197
							cycle_counter <= 0;
198
							control_state <= FSI_INITIALIZE_STATE_03;
199 200
						end else begin
							cycle_counter <= cycle_counter - 1;
201 202 203 204 205 206 207 208 209 210 211 212 213 214
						end
					end else begin
						// Should never reach this state
						cycle_error_reg <= FSI_ERROR_INTERNAL_FAULT;
						control_state <= FSI_INITIALIZE_STATE_01;
					end
				end
				FSI_INITIALIZE_STATE_03: begin
					// Transmission complete, switch direction
					fsi_data_reg_internal = 0;

					if (cycle_counter >= (FSI_TURNAROUND_CYCLES - 1)) begin
						timeout_counter <= 0;
						ipoll_start_timer <= 0;
215
						fsi_data_direction_reg <= 0;
216 217 218 219 220 221 222
						if (internal_cmd_issue_delay_reg > 0) begin
							delay_counter <= 1;
							post_delay_control_state <= FSI_TRANSFER_STATE_IDLE;
							control_state <= FSI_TRANSFER_STATE_DL01;
						end else begin
							control_state <= FSI_TRANSFER_STATE_IDLE;
						end
223 224
					end else begin
						cycle_counter <= cycle_counter + 1;
225 226 227
					end
				end
				FSI_TRANSFER_STATE_IDLE: begin
228
					if (busy_response_in_process
229
						&& ((enable_ipoll && (commands_since_last_ipoll < FSI_IPOLL_MAX_SEQ_STD_COMMANDS)) || !enable_ipoll)) begin
230 231
						commands_since_last_ipoll <= commands_since_last_ipoll + 1;
						ipoll_in_process <= 0;
232
						crc_data <= 0;
233
						control_state <= FSI_TRANSFER_STATE_TX01;
234
					end else if (start_cycle
235
						&& ((enable_ipoll && (commands_since_last_ipoll < FSI_IPOLL_MAX_SEQ_STD_COMMANDS)) || !enable_ipoll)) begin
236 237 238
						data_direction_reg <= data_direction;
						data_length_reg <= data_length;
						slave_id_reg <= slave_id;
239
						case (data_length_reg)
240 241 242 243 244 245
							0: address_reg <= address[20:0];
							1: address_reg <= {address[20:1], 1'b0};
							2: address_reg <= {address[20:2], 2'b01};
							default: address_reg <= address[20:0];
						endcase
						tx_data_reg <= tx_data;
246
						enable_relative_address_reg <= enable_relative_address;
247
						enable_extended_address_mode_reg <= enable_extended_address_mode;
248
						enable_crc_protection_reg <= enable_crc_protection;
249 250 251 252
						enhanced_error_recovery_reg <= enhanced_error_recovery;
						slave_error_recovery_state <= 0;
						master_error_recovery_state <= 0;
						fsi_command_code_set <= 0;
253
						ipoll_in_process <= 0;
254 255 256 257 258 259 260 261
						crc_data <= 0;
						cycle_error_reg <= FSI_ERROR_NONE;
						fsi_master_timeout_counting <= 0;
						commands_since_last_ipoll <= commands_since_last_ipoll + 1;
						control_state <= FSI_TRANSFER_STATE_TX01;
					end else if (enable_ipoll && ((ipoll_start_timer > FSI_IPOLL_IDLE_START_CYCLES)
						|| (commands_since_last_ipoll >= FSI_IPOLL_MAX_SEQ_STD_COMMANDS))) begin
						// Send I_POLL
262
						//
263 264 265 266 267 268
						// NOTE: IPOLL requests can override any other incoming command requests.
						// if no IPOLL has been issued for the past FSI_IPOLL_MAX_SEQ_STD_COMMANDS
						// number of command requests.  This is to ensure that interrupts are not
						// lost under heavy I/O load.
						if (enable_ipoll) begin
							fsi_command_code <= FSI_CODEWORD_TX_MSG_I_POLL_DAT;
269
							fsi_command_code_length <= FSI_CODEWORD_TX_MSG_I_POLL_LEN;
270 271 272 273 274 275 276 277 278 279 280 281 282 283 284
							cycle_counter <= FSI_CODEWORD_TX_MSG_I_POLL_LEN;
							fsi_command_code_set <= 1;
							ipoll_in_process <= 1;
							crc_data <= 0;
							control_state <= FSI_TRANSFER_STATE_TX01;
						end
						commands_since_last_ipoll <= 0;
						ipoll_start_timer <= 0;
					end else begin
						ipoll_in_process <= 0;
						ipoll_start_timer <= ipoll_start_timer + 1;
					end
					if (!enable_ipoll) begin
						ipoll_error_reg <= 0;
					end
285
					internal_cmd_issue_delay_reg <= internal_cmd_issue_delay;
286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307
					cycle_complete_reg <= 0;
				end
				FSI_TRANSFER_STATE_TX01: begin
					// Send start bit
					fsi_data_direction_reg <= 1;
					crc_protected_bits_transmitting = 1;
					fsi_data_reg_internal = 1;
					control_state <= FSI_TRANSFER_STATE_TX02;
				end
				FSI_TRANSFER_STATE_TX02: begin
					// Send slave ID bit 1
					fsi_data_direction_reg <= 1;
					crc_protected_bits_transmitting = 1;
					fsi_data_reg_internal = slave_id_reg[1];
					control_state <= FSI_TRANSFER_STATE_TX03;
				end
				FSI_TRANSFER_STATE_TX03: begin
					// Send slave ID bit 2
					fsi_data_direction_reg <= 1;
					crc_protected_bits_transmitting = 1;
					fsi_data_reg_internal = slave_id_reg[0];
					if (!fsi_command_code_set) begin
308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323
						if (enable_relative_address_reg) begin
							if (last_address_valid && (last_address[20:2] == address_reg[20:2])) begin
								fsi_command_code <= FSI_CODEWORD_TX_MSG_SAME_ADR_DAT;
								fsi_command_code_length <= FSI_CODEWORD_TX_MSG_SAME_ADR_LEN;
								cycle_counter <= FSI_CODEWORD_TX_MSG_SAME_ADR_LEN;
							end else if (last_address_valid && (last_address[20:8] == address_reg[20:8])) begin
								fsi_command_code <= FSI_CODEWORD_TX_MSG_REL_ADR_DAT;
								fsi_command_code_length <= FSI_CODEWORD_TX_MSG_REL_ADR_LEN;
								cycle_counter <= FSI_CODEWORD_TX_MSG_REL_ADR_LEN;
								if (address_reg < last_address) begin
									fsi_rel_address_delta_negative <= 1;
								end else begin
									fsi_rel_address_delta_negative <= 0;
								end
								// Relative delta is actually 9-bit two's complement, but fsi_rel_address_delta_negative is used as bit 8
								fsi_rel_address_delta = address_reg - last_address;
324
							end else begin
325 326 327
								fsi_command_code <= FSI_CODEWORD_TX_MSG_ABS_ADR_DAT;
								fsi_command_code_length <= FSI_CODEWORD_TX_MSG_ABS_ADR_LEN;
								cycle_counter <= FSI_CODEWORD_TX_MSG_ABS_ADR_LEN;
328 329 330
							end
						end else begin
							fsi_command_code <= FSI_CODEWORD_TX_MSG_ABS_ADR_DAT;
331
							fsi_command_code_length <= FSI_CODEWORD_TX_MSG_ABS_ADR_LEN;
332 333 334 335 336 337 338 339 340 341 342 343 344 345
							cycle_counter <= FSI_CODEWORD_TX_MSG_ABS_ADR_LEN;
						end
						fsi_command_code_set <= 1;
					end
					control_state <= FSI_TRANSFER_STATE_TX04;
				end
				FSI_TRANSFER_STATE_TX04: begin
					// Send command code
					if (cycle_counter > 0) begin
						fsi_data_direction_reg <= 1;
						crc_protected_bits_transmitting = 1;
						fsi_data_reg_internal = fsi_command_code[cycle_counter-1];
						cycle_counter <= cycle_counter - 1;
						if (cycle_counter == 1) begin
346 347 348 349
							if (((fsi_command_code == FSI_CODEWORD_TX_MSG_D_POLL_DAT) && (fsi_command_code_length == FSI_CODEWORD_TX_MSG_D_POLL_LEN))
								|| ((fsi_command_code == FSI_CODEWORD_TX_MSG_E_POLL_DAT) && (fsi_command_code_length == FSI_CODEWORD_TX_MSG_E_POLL_LEN))
								|| ((fsi_command_code == FSI_CODEWORD_TX_MSG_I_POLL_DAT) && (fsi_command_code_length == FSI_CODEWORD_TX_MSG_I_POLL_LEN))
								|| ((fsi_command_code == FSI_CODEWORD_TX_MSG_TERM_DAT) && (fsi_command_code_length == FSI_CODEWORD_TX_MSG_TERM_LEN))) begin
350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367
								cycle_counter <= 4;
								control_state <= FSI_TRANSFER_STATE_TX09;
							end else begin
								control_state <= FSI_TRANSFER_STATE_TX05;
							end
						end
					end else begin
						// Should never reach this state
						cycle_error_reg <= FSI_ERROR_INTERNAL_FAULT;
						control_state <= FSI_INITIALIZE_STATE_01;
					end
				end
				FSI_TRANSFER_STATE_TX05: begin
					// Send read/write flag
					fsi_data_direction_reg <= 1;
					crc_protected_bits_transmitting = 1;
					fsi_data_reg_internal = ~data_direction_reg;
					control_state <= FSI_TRANSFER_STATE_TX06;
368
					if ((fsi_command_code == FSI_CODEWORD_TX_MSG_SAME_ADR_DAT) && (fsi_command_code_length == FSI_CODEWORD_TX_MSG_SAME_ADR_LEN)) begin
369 370
						address_tx_reg <= address_reg;
						cycle_counter <= 2;
371
					end else if ((fsi_command_code == FSI_CODEWORD_TX_MSG_REL_ADR_DAT) && (fsi_command_code_length == FSI_CODEWORD_TX_MSG_REL_ADR_LEN)) begin
372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392
						// Set up bit 8 of the address as the sign bit per the specification.
						//
						// NOTE: The specification is unclear about the meaning of the sign bit,
						// so assume conventional sign bit semantics (1 == negative).
						address_tx_reg <= {address_reg[20:9], fsi_rel_address_delta_negative, fsi_rel_address_delta[7:0]};
						cycle_counter <= 9;
					end else begin
						address_tx_reg <= address_reg;
						cycle_counter <= 21;
					end
				end
				FSI_TRANSFER_STATE_TX06: begin
					// Send address
					if (cycle_counter > 0) begin
						fsi_data_direction_reg <= 1;
						crc_protected_bits_transmitting = 1;
						fsi_data_reg_internal = address_tx_reg[cycle_counter-1];
						cycle_counter <= cycle_counter - 1;
						if (cycle_counter == 1) begin
							control_state <= FSI_TRANSFER_STATE_TX07;
						end
393 394 395 396 397 398 399 400

						// Force lowest address bits to specification-mandated values if required
						case (data_length_reg)
							0: address_tx_reg <= address_tx_reg[20:0];
							1: address_tx_reg <= {address_tx_reg[20:1], 1'b0};
							2: address_tx_reg <= {address_tx_reg[20:2], 2'b01};
							default: address_tx_reg <= address_tx_reg[20:0];
						endcase
401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484
					end else begin
						// Should never reach this state
						cycle_error_reg <= FSI_ERROR_INTERNAL_FAULT;
						control_state <= FSI_INITIALIZE_STATE_01;
					end
				end
				FSI_TRANSFER_STATE_TX07: begin
					// Send data size bit
					fsi_data_direction_reg <= 1;
					crc_protected_bits_transmitting = 1;
					case (data_length_reg)
						0: fsi_data_reg_internal = 0;
						1: fsi_data_reg_internal = 1;
						2: fsi_data_reg_internal = 1;
						default: fsi_data_reg_internal = 0;
					endcase
					if (data_direction_reg) begin
						// Write
						case (data_length_reg)
							0: begin
								// Byte transfer
								cycle_counter <= 8;
							end
							1: begin
								// Half word transfer
								cycle_counter <= 16;
							end
							2: begin
								// Word transfer
								cycle_counter <= 32;
							end
							default: begin
								// Invalid sizes are treated as byte transfers
								cycle_counter <= 8;
							end
						endcase
						control_state <= FSI_TRANSFER_STATE_TX08;
					end else begin
						// Read
						cycle_counter <= 4;
						control_state <= FSI_TRANSFER_STATE_TX09;
					end
				end
				FSI_TRANSFER_STATE_TX08: begin
					// Send data
					if (cycle_counter > 0) begin
						fsi_data_direction_reg <= 1;
						crc_protected_bits_transmitting = 1;
						fsi_data_reg_internal = tx_data_reg[cycle_counter-1];
						cycle_counter <= cycle_counter - 1;
						if (cycle_counter == 1) begin
							cycle_counter <= 4;
							control_state <= FSI_TRANSFER_STATE_TX09;
						end
					end else begin
						// Should never reach this state
						cycle_error_reg <= FSI_ERROR_INTERNAL_FAULT;
						control_state <= FSI_INITIALIZE_STATE_01;
					end
				end
				FSI_TRANSFER_STATE_TX09: begin
					// Send CRC
					if (cycle_counter > 0) begin
						fsi_data_direction_reg <= 1;
						crc_protected_bits_transmitting = 0;
						fsi_data_reg_internal = crc_data[cycle_counter-1];
						cycle_counter <= cycle_counter - 1;
						if (cycle_counter == 1) begin
							control_state <= FSI_TRANSFER_STATE_TX10;
						end
					end else begin
						// Should never reach this state
						cycle_error_reg <= FSI_ERROR_INTERNAL_FAULT;
						control_state <= FSI_INITIALIZE_STATE_01;
					end
				end
				FSI_TRANSFER_STATE_TX10: begin
					// Transmission complete, switch direction
					fsi_data_reg_internal = 0;

					if (cycle_counter >= (FSI_TURNAROUND_CYCLES - 1)) begin
						timeout_counter <= 0;
						rx_data_reg <= 0;
						crc_data <= 0;
485
						fsi_data_direction_reg <= 0;
486
						control_state <= FSI_TRANSFER_STATE_TX11;
487 488
					end else begin
						cycle_counter <= cycle_counter + 1;
489 490 491 492 493 494
					end
				end
				FSI_TRANSFER_STATE_TX11: begin
					// Wait for start signal
					if (fsi_data_in_internal) begin
						crc_protected_bits_receiving = 1;
495 496 497 498 499
						if (enable_extended_address_mode_reg) begin
							control_state <= FSI_TRANSFER_STATE_RX03;
						end else begin
							control_state <= FSI_TRANSFER_STATE_RX01;
						end
500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549
					end else begin
						if (timeout_counter >= (FSI_TIMEOUT_CYCLES - 1)) begin
							if (ipoll_in_process) begin
								ipoll_error_reg <= 1;
							end else begin
								cycle_error_reg <= FSI_ERROR_TIMEOUT;
							end
							fsi_master_timeout_counting <= 0;
							control_state <= FSI_TRANSFER_STATE_TR01;
						end else begin
							timeout_counter <= timeout_counter + 1;
						end
					end
				end
				FSI_TRANSFER_STATE_RX01: begin
					// Receive slave ID, bit 1
					crc_protected_bits_receiving = 1;
					rx_slave_id[1] <= fsi_data_in_internal;
					control_state <= FSI_TRANSFER_STATE_RX02;
				end
				FSI_TRANSFER_STATE_RX02: begin
					// Receive slave ID, bit 2
					crc_protected_bits_receiving = 1;
					rx_slave_id[0] <= fsi_data_in_internal;
					control_state <= FSI_TRANSFER_STATE_RX03;
				end
				FSI_TRANSFER_STATE_RX03: begin
					// Receive message type, bit 1
					crc_protected_bits_receiving = 1;
					if (ipoll_in_process) begin
						if (fsi_data_in_internal) begin
							// IPOLL response has one bit reserved for type
							// If that bit is not zero, the response is not a valid I_POLL_RSP message
							ipoll_error_reg <= 1;
							control_state <= FSI_TRANSFER_STATE_TR01;
						end else begin
							// Potentially valid I_POLL_RSP message
							control_state <= FSI_TRANSFER_STATE_IR01;
						end
					end else begin
						rx_message_type[1] <= fsi_data_in_internal;
						control_state <= FSI_TRANSFER_STATE_RX04;
					end
				end
				FSI_TRANSFER_STATE_RX04: begin
					// Receive message type, bit 2
					crc_protected_bits_receiving = 1;
					rx_message_type[0] <= fsi_data_in_internal;
					case ({rx_message_type[1], fsi_data_in_internal})
						FSI_CODEWORD_RX_MSG_ACK: begin
550 551
							if ((fsi_command_code == FSI_CODEWORD_TX_MSG_TERM_DAT) && (fsi_command_code_length == FSI_CODEWORD_TX_MSG_TERM_LEN)) begin
								// TERM command sent -- parse ACK message
552 553 554
								cycle_counter <= 4;
								control_state <= FSI_TRANSFER_STATE_RX06;
							end else begin
555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581
								if (data_direction_reg) begin
									// Write -- ACK message
									cycle_counter <= 4;
									control_state <= FSI_TRANSFER_STATE_RX06;
								end else begin
									// Read -- ACK_D message
									case (data_length_reg)
										0: begin
											// Byte transfer
											cycle_counter <= 8;
										end
										1: begin
											// Half word transfer
											cycle_counter <= 16;
										end
										2: begin
											// Word transfer
											cycle_counter <= 32;
										end
										default: begin
											// Invalid sizes are treated as byte transfers
											cycle_counter <= 8;
										end
									endcase
									slave_error_recovery_state <= 0;
									control_state <= FSI_TRANSFER_STATE_RX05;
								end
582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609
							end
						end
						FSI_CODEWORD_RX_MSG_BUSY: begin
							if (ipoll_in_process) begin
								// BUSY not allowed as IPOLL response!
								ipoll_error_reg <= 1;
								control_state <= FSI_TRANSFER_STATE_TR01;
							end else begin
								fsi_master_timeout_counting <= 1;
								slave_error_recovery_state <= 0;
								cycle_counter <= 4;
								control_state <= FSI_TRANSFER_STATE_RX06;
							end
						end
						FSI_CODEWORD_RX_MSG_ERR_A: begin
							// Slave received corrupted message from master and does not support enhanced error recovery
							if (ipoll_in_process) begin
								ipoll_error_reg <= 1;
							end else begin
								cycle_error_reg <= FSI_ERROR_BAD_TX_CHECKSUM;
							end
							control_state <= FSI_TRANSFER_STATE_TR01;
						end
						FSI_CODEWORD_RX_MSG_ERR_C: begin
							// Slave received corrupted message from master and is requesting enhanced error recovery
							if (enhanced_error_recovery_reg[0] && (slave_error_recovery_state == 0)) begin
								// Configure state machine to resend command message
								slave_error_recovery_state <= 1;
610 611
								cycle_counter <= 4;
								control_state <= FSI_TRANSFER_STATE_RX06;
612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669
							end else begin
								// Master does not support enhanced error recovery or error recovery fauled
								if (ipoll_in_process) begin
									ipoll_error_reg <= 1;
								end else begin
									cycle_error_reg <= FSI_ERROR_BAD_TX_CHECKSUM;
								end
								control_state <= FSI_TRANSFER_STATE_TR01;
							end
						end
						default: begin
							// NOTE: This could be the result of data corruption!
							// Unfortunately, since the response messages are variable length, there is no
							// way to know the intended message length and therefore no way to run checksum
							// validation at this early stage...
							slave_error_recovery_state <= 0;
							if (ipoll_in_process) begin
								ipoll_error_reg <= 1;
							end else begin
								cycle_error_reg <= FSI_ERROR_INVALID_CODEWORD;
							end
							control_state <= FSI_TRANSFER_STATE_TR01;
						end
					endcase
				end
				FSI_TRANSFER_STATE_RX05: begin
					// Receive data
					if (cycle_counter > 0) begin
						crc_protected_bits_receiving = 1;
						rx_data_reg[cycle_counter-1] = fsi_data_in_internal;
						cycle_counter <= cycle_counter - 1;
						if (cycle_counter == 1) begin
							cycle_counter <= 4;
							control_state <= FSI_TRANSFER_STATE_RX06;
						end
					end else begin
						// Should never reach this state
						cycle_error_reg <= FSI_ERROR_INTERNAL_FAULT;
						control_state <= FSI_INITIALIZE_STATE_01;
					end
				end
				FSI_TRANSFER_STATE_RX06: begin
					// Receive CRC
					if (cycle_counter > 0) begin
						// Load CRC bits into Galios LFSR for verification
						crc_protected_bits_receiving = 1;
						cycle_counter <= cycle_counter - 1;
						if (cycle_counter == 1) begin
							control_state <= FSI_TRANSFER_STATE_RX07;
						end
					end else begin
						// Should never reach this state
						cycle_error_reg <= FSI_ERROR_INTERNAL_FAULT;
						control_state <= FSI_INITIALIZE_STATE_01;
					end
				end
				FSI_TRANSFER_STATE_RX07: begin
					crc_protected_bits_receiving = 0;
670
					if ((crc_data != 0) && enable_crc_protection_reg) begin
671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687
						// Master received corrupted message from slave
						if (((enhanced_error_recovery_reg[1] && ipoll_in_process)
							|| (enhanced_error_recovery_reg[0] && !ipoll_in_process))
							&& (master_error_recovery_state == 0)) begin
							// Configure state machine to send E_POLL
							master_error_recovery_state <= 1;
							control_state <= FSI_TRANSFER_STATE_TR01;
						end else begin
							// Master does not support enhanced error recovery or error recovery failed
							if (ipoll_in_process) begin
								ipoll_error_reg <= 1;
							end else begin
								cycle_error_reg <= FSI_ERROR_BAD_RX_CHECKSUM;
							end
							control_state <= FSI_TRANSFER_STATE_TR01;
						end
					end else begin
688
						if (!enable_extended_address_mode_reg && (rx_slave_id != slave_id_reg)) begin
689 690 691 692 693 694
							// Slave message was not meant for this master
							// Keep listening, but do not reset timeout counter here!
							rx_data_reg <= 0;
							crc_data <= 0;
							control_state <= FSI_TRANSFER_STATE_TX11;
						end else begin
695 696 697 698
							if (ipoll_in_process) begin
								interrupt_field_reg <= interrupt_field_internal;
								dma_control_field_reg <= dma_control_field_internal;
							end
699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717
							master_error_recovery_state <= 0;
							control_state <= FSI_TRANSFER_STATE_TR01;
						end
					end
				end
				FSI_TRANSFER_STATE_TR01: begin
					// Reception complete, switch direction
					fsi_data_reg_internal = 0;

					// Stop CRC generation
					crc_protected_bits_transmitting = 0;
					crc_protected_bits_receiving = 0;

					if (cycle_counter >= (FSI_TURNAROUND_CYCLES - 1)) begin
						if (slave_error_recovery_state == 1) begin
							// Resend command
							fsi_command_code_set <= 0;
							crc_data <= 0;
							slave_error_recovery_state <= 2;
718 719 720 721 722 723 724
							if (internal_cmd_issue_delay_reg > 0) begin
								delay_counter <= 1;
								post_delay_control_state <= FSI_TRANSFER_STATE_TX01;
								control_state <= FSI_TRANSFER_STATE_DL01;
							end else begin
								control_state <= FSI_TRANSFER_STATE_TX01;
							end
725 726 727
						end else if (master_error_recovery_state == 1) begin
							// Send E_POLL
							fsi_command_code <= FSI_CODEWORD_TX_MSG_E_POLL_DAT;
728
							fsi_command_code_length <= FSI_CODEWORD_TX_MSG_E_POLL_LEN;
729 730 731 732
							cycle_counter <= FSI_CODEWORD_TX_MSG_E_POLL_LEN;
							fsi_command_code_set <= 1;
							crc_data <= 0;
							master_error_recovery_state <= 2;
733 734 735 736 737 738 739
							if (internal_cmd_issue_delay_reg > 0) begin
								delay_counter <= 1;
								post_delay_control_state <= FSI_TRANSFER_STATE_TX01;
								control_state <= FSI_TRANSFER_STATE_DL01;
							end else begin
								control_state <= FSI_TRANSFER_STATE_TX01;
							end
740 741 742 743 744
						end else if (cycle_error_reg == FSI_ERROR_NONE) begin
							if (rx_message_type == FSI_CODEWORD_RX_MSG_BUSY) begin
								if (fsi_master_timeout_counter < FSI_MASTER_TIMEOUT_CYCLES) begin
									// Send D_POLL
									fsi_command_code <= FSI_CODEWORD_TX_MSG_D_POLL_DAT;
745
									fsi_command_code_length <= FSI_CODEWORD_TX_MSG_D_POLL_LEN;
746 747
									cycle_counter <= FSI_CODEWORD_TX_MSG_D_POLL_LEN;
									fsi_command_code_set <= 1;
748
									busy_response_in_process <= 1;
749
									crc_data <= 0;
750 751 752 753 754 755 756
									if (internal_cmd_issue_delay_reg > 0) begin
										delay_counter <= 1;
										post_delay_control_state <= FSI_TRANSFER_STATE_IDLE;
										control_state <= FSI_TRANSFER_STATE_DL01;
									end else begin
										control_state <= FSI_TRANSFER_STATE_IDLE;
									end
757 758 759
								end else begin
									// Send TERM
									fsi_command_code <= FSI_CODEWORD_TX_MSG_TERM_DAT;
760
									fsi_command_code_length <= FSI_CODEWORD_TX_MSG_TERM_LEN;
761 762 763 764 765 766 767 768
									cycle_counter <= FSI_CODEWORD_TX_MSG_TERM_LEN;
									if (ipoll_in_process) begin
										ipoll_error_reg <= 1;
									end else begin
										cycle_error_reg <= FSI_ERROR_MASTER_TIMEOUT;
									end
									fsi_master_timeout_counting <= 0;
									fsi_command_code_set <= 1;
769
									busy_response_in_process <= 0;
770
									crc_data <= 0;
771 772 773 774 775 776 777
									if (internal_cmd_issue_delay_reg > 0) begin
										delay_counter <= 1;
										post_delay_control_state <= FSI_TRANSFER_STATE_TX01;
										control_state <= FSI_TRANSFER_STATE_DL01;
									end else begin
										control_state <= FSI_TRANSFER_STATE_TX01;
									end
778 779 780 781
								end
							end else begin
								// Transfer complete!
								if (!ipoll_in_process) begin
782
									rx_data <= rx_data_reg;
783 784
									cycle_complete_reg <= 1;
								end
785
								busy_response_in_process <= 0;
786 787 788 789 790 791 792 793 794 795
								fsi_master_timeout_counting <= 0;
								control_state <= FSI_TRANSFER_STATE_TR02;
							end
							slave_error_recovery_state <= 0;
							master_error_recovery_state <= 0;
						end else begin
							// Transfer failed!
							if (!ipoll_in_process) begin
								cycle_complete_reg <= 1;
							end
796
							busy_response_in_process <= 0;
797 798 799 800 801
							fsi_master_timeout_counting <= 0;
							control_state <= FSI_TRANSFER_STATE_TR02;
							slave_error_recovery_state <= 0;
							master_error_recovery_state <= 0;
						end
802 803 804
						fsi_data_direction_reg <= 0;
					end else begin
						cycle_counter <= cycle_counter + 1;
805 806 807
					end
				end
				FSI_TRANSFER_STATE_TR02: begin
808
					if (!start_cycle || ipoll_in_process) begin
809
						if (cycle_error_reg == FSI_ERROR_NONE) begin
810
							last_address <= address_tx_reg;
811 812 813 814 815
							last_address_valid <= 1;
						end else begin
							last_address_valid <= 0;
						end
						ipoll_start_timer <= 0;
816
						ipoll_in_process <= 0;
817 818 819 820 821 822 823
						if (internal_cmd_issue_delay_reg > 0) begin
							delay_counter <= 1;
							post_delay_control_state <= FSI_TRANSFER_STATE_IDLE;
							control_state <= FSI_TRANSFER_STATE_DL01;
						end else begin
							control_state <= FSI_TRANSFER_STATE_IDLE;
						end
824 825 826 827 828
					end
				end
				FSI_TRANSFER_STATE_IR01: begin
					// Receive interrupt field, bit 1
					crc_protected_bits_receiving = 1;
829
					interrupt_field_internal[1] <= fsi_data_in_internal;
830 831 832 833 834
					control_state <= FSI_TRANSFER_STATE_IR02;
				end
				FSI_TRANSFER_STATE_IR02: begin
					// Receive interrupt field, bit 2
					crc_protected_bits_receiving = 1;
835
					interrupt_field_internal[0] <= fsi_data_in_internal;
836 837 838 839 840
					control_state <= FSI_TRANSFER_STATE_IR03;
				end
				FSI_TRANSFER_STATE_IR03: begin
					// Receive DMA control field, bit 1
					crc_protected_bits_receiving = 1;
841
					dma_control_field_internal[2] <= fsi_data_in_internal;
842 843 844 845 846
					control_state <= FSI_TRANSFER_STATE_IR04;
				end
				FSI_TRANSFER_STATE_IR04: begin
					// Receive DMA control field, bit 2
					crc_protected_bits_receiving = 1;
847
					dma_control_field_internal[1] <= fsi_data_in_internal;
848 849 850 851 852
					control_state <= FSI_TRANSFER_STATE_IR05;
				end
				FSI_TRANSFER_STATE_IR05: begin
					// Receive DMA control field, bit 3
					crc_protected_bits_receiving = 1;
853
					dma_control_field_internal[0] <= fsi_data_in_internal;
854 855 856
					cycle_counter <= 4;
					control_state <= FSI_TRANSFER_STATE_RX06;
				end
857 858 859 860 861 862 863
				FSI_TRANSFER_STATE_DL01: begin
					if (delay_counter >= internal_cmd_issue_delay_reg) begin
						control_state <= post_delay_control_state;
					end else begin
						delay_counter <= delay_counter + 1;
					end
				end
864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896
				default: begin
					// Should never reach this state
					cycle_error_reg <= FSI_ERROR_INTERNAL_FAULT;
					control_state <= FSI_INITIALIZE_STATE_01;
				end
			endcase
		end

		// CRC calculation
		// Implement Galios-type LFSR for polynomial 0x7 (MSB first)
		if (crc_protected_bits_transmitting) begin
			crc_feedback = crc_data[3] ^ fsi_data_reg_internal;
		end
		if (crc_protected_bits_receiving) begin
			crc_feedback = crc_data[3] ^ fsi_data_in_internal;
		end
		if (crc_protected_bits_transmitting || crc_protected_bits_receiving) begin
			crc_data[0] <= crc_feedback;
			crc_data[1] <= crc_data[0] ^ crc_feedback;
			crc_data[2] <= crc_data[1] ^ crc_feedback;
			crc_data[3] <= crc_data[2];
		end

		// Transmit data
		fsi_data_reg <= fsi_data_reg_internal;

		if (fsi_master_timeout_counting) begin
			fsi_master_timeout_counter <= fsi_master_timeout_counter + 1;
		end else begin
			fsi_master_timeout_counter <= 0;
		end
	end
endmodule