Commit ffd86801 authored by Patrick Williams's avatar Patrick Williams Committed by GitHub

Merge pull request #3 from dgilbert999/gcc-4_9_2-ppe42

Fix compile issue when compiling with gcc 6
parents d8a1bac8 565c21a4
......@@ -39,11 +39,11 @@
#endif
#if TARGET_DEFAULT & OPTION_MASK_64BIT
#define OPT_ARCH64 "!"OPT_32
#define OPT_ARCH64 "!" OPT_32
#define OPT_ARCH32 OPT_32
#else
#define OPT_ARCH64 OPT_64
#define OPT_ARCH32 "!"OPT_64
#define OPT_ARCH32 "!" OPT_64
#endif
/* Support for a compile-time default CPU, et cetera. The rules are:
......
......@@ -1025,12 +1025,30 @@
(const_int 0)))]
"")
;; PPE42 does not support lbzux instruction
(define_insn ""
[(set (match_operand:HI 0 "gpc_reg_operand" "=r")
(zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m")))]
"(rs6000_cpu == PROCESSOR_PPE42) &&
update_indexed_address_mem (operands[1], VOIDmode)"
"*
{
{
static char buf[40];
int r1 = REGNO(XEXP(XEXP(operands[1],0),0));
sprintf(buf,\"add %d,%%1 #lbzux\;lbz %%0,0(%d)\",r1,r1);
return buf;
}
}"
[(set_attr "type" "load_ux")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
(zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
""
"@
lbz%U1%X1 %0,%1 #DEBUGME 2 %1
lbz%U1%X1 %0,%1
rlwinm %0,%1,0,0xff"
[(set_attr_alternative "type"
[(if_then_else
......@@ -1159,6 +1177,24 @@
""
"")
;; PPE42 does not support lhzux instruction
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m")))]
"(rs6000_cpu == PROCESSOR_PPE42) &&
update_indexed_address_mem (operands[1], VOIDmode)"
"*
{
{
static char buf[40];
int r1 = REGNO(XEXP(XEXP(operands[1],0),0));
sprintf(buf,\"add %d,%%1 #lhzux\;lhz %%0,0(%d)\",r1,r1);
return buf;
}
}"
[(set_attr "type" "load_ux")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
......@@ -2310,7 +2346,7 @@
;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
;; (zero_extend:SI
;; (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
;; ""
;; "rs6000_cpu != PROCESSOR_PPE42"
;; "lhbrx %0,%y1"
;; [(set_attr "length" "4")
;; (set_attr "type" "load")])
......@@ -2331,7 +2367,7 @@
;; (bswap:HI
;; (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
;; (clobber (match_scratch:SI 2 "=X,X,&r"))]
;; ""
;; "rs6000_cpu != PROCESSOR_PPE42"
;; "@
;; lhbrx %0,%y1
;; sthbrx %1,%y0
......@@ -2386,7 +2422,7 @@
;; [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
;; (bswap:SI
;; (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
;; ""
;; "rs6000_cpu != PROCESSOR_PPE42"
;; "@
;; lwbrx %0,%y1
;; stwbrx %1,%y0
......@@ -9116,6 +9152,45 @@
(const_int 0)))]
"")
;; ppe42 does not support lhzux instruction
(define_insn "*movhi_internal_load"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r")
(match_operand:HI 1 "input_operand" "m"))]
"rs6000_cpu == PROCESSOR_PPE42 &&
gpc_reg_operand (operands[0], HImode) &&
update_indexed_address_mem (operands[1], VOIDmode)"
"*
{
{
static char buf[40];
int r1 = REGNO(XEXP(XEXP(operands[1],0),0));
sprintf(buf,\"add %d,%%1 #lhzux\;lhz %%0,0(%d)\",r1,r1);
return buf;
}
}"
[(set_attr "type" "load_ux")
(set_attr "length" "8")])
;; ppe42 does not support sthux instruction
(define_insn "*movhi_internal_store"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m")
(match_operand:HI 1 "input_operand" "r"))]
"rs6000_cpu == PROCESSOR_PPE42 &&
gpc_reg_operand (operands[1], HImode) &&
update_indexed_address_mem (operands[0], VOIDmode)"
"*
{
{
static char buf[40];
int r1 = REGNO(XEXP(XEXP(operands[0],0),0));
sprintf(buf,\"add %d,%%0 #sthux\;sth %%1,0(%d)\",r1,r1);
return buf;
}
}"
[(set_attr "type" "store_ux")
(set_attr "length" "8")])
(define_insn "*movhi_internal"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
(match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
......@@ -9156,6 +9231,45 @@
""
"{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
;; ppe42 does not support lbzux
(define_insn "*movqi_internal_1oad"
[(set (match_operand:QI 0 "nonimmediate_operand" "=r")
(match_operand:QI 1 "input_operand" "m"))]
"(rs6000_cpu == PROCESSOR_PPE42) &&
gpc_reg_operand (operands[0], QImode) &&
update_indexed_address_mem (operands[1], VOIDmode)"
"*
{
{
static char buf[40];
int r1 = REGNO(XEXP(XEXP(operands[1],0),0));
sprintf(buf,\"add %d,%%1 #lbzux\;lbz %%0,0(%d)\",r1,r1);
return buf;
}
}"
[(set_attr "type" "load_ux")
(set_attr "length" "8")])
;; ppe42 does not support stbux
(define_insn "*movqi_internal_store"
[(set (match_operand:QI 0 "nonimmediate_operand" "=m")
(match_operand:QI 1 "input_operand" "r"))]
"(rs6000_cpu == PROCESSOR_PPE42) &&
gpc_reg_operand (operands[1], QImode) &&
update_indexed_address_mem (operands[0], VOIDmode)"
"*
{
{
static char buf[40];
int r1 = REGNO(XEXP(XEXP(operands[0],0),0));
sprintf(buf,\"add %d,%%0 #stbux\;stb %%1,0(%d)\",r1,r1);
return buf;
}
}"
[(set_attr "type" "store_ux")
(set_attr "length" "8")])
(define_insn "*movqi_internal"
[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
(match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
......@@ -9163,7 +9277,7 @@
|| gpc_reg_operand (operands[1], QImode)"
"@
mr %0,%1
lbz%U1%X1 %0,%1 #DEBUGME 3 %1
lbz%U1%X1 %0,%1
stb%U0%X0 %1,%0
li %0,%1
mf%1 %0
......
......@@ -21,7 +21,7 @@ __inline
#endif
static unsigned int hash (const char *, unsigned int);
#ifdef __GNUC__
__inline
//__inline
#endif
const char * libc_name_p (const char *, unsigned int);
%}
......
......@@ -52,7 +52,7 @@ __inline
#endif
static unsigned int hash (const char *, unsigned int);
#ifdef __GNUC__
__inline
//__inline
#endif
const char * libc_name_p (const char *, unsigned int);
/* maximum key range = 391, duplicates = 0 */
......
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