Commit ebbb7f00 authored by wschmidt's avatar wschmidt

2014-04-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com>

	PR target/60839
	Revert the following patch

	2014-04-02  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/60735
	* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have
	software floating point or no floating point registers, do not
	allow any type in the FPRs.  Eliminate a test for SPE SIMD types
	in GPRs that occurs after we tested for GPRs that would never be
	true.

	* config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):
	Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,
	since the FMOVE64 type is DFmode/DDmode.  If TARGET_E500_DOUBLE,
	specifically allow DDmode, since that does not use the SPE SIMD
	instructions.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@209426 138bc75d-0d04-0410-961f-82ee72b054a4
parent 251bd74c
2014-04-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/60839
Revert the following patch
2014-04-02 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/60735
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have
software floating point or no floating point registers, do not
allow any type in the FPRs. Eliminate a test for SPE SIMD types
in GPRs that occurs after we tested for GPRs that would never be
true.
* config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):
Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,
since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE,
specifically allow DDmode, since that does not use the SPE SIMD
instructions.
2014-04-15 Jakub Jelinek <jakub@redhat.com>
PR plugins/59335
......
......@@ -1752,9 +1752,6 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
modes and DImode. */
if (FP_REGNO_P (regno))
{
if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
return 0;
if (SCALAR_FLOAT_MODE_P (mode)
&& (mode != TDmode || (regno % 2) == 0)
&& FP_REGNO_P (last_regno))
......@@ -1783,6 +1780,10 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
|| mode == V1TImode);
/* ...but GPRs can hold SIMD data on the SPE in one register. */
if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
return 1;
/* We cannot put non-VSX TImode or PTImode anywhere except general register
and it must be able to fit within the register set. */
......
......@@ -9394,9 +9394,8 @@
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
(match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
"! TARGET_POWERPC64
&& ((TARGET_FPRS && TARGET_DOUBLE_FLOAT)
|| TARGET_SOFT_FLOAT
|| (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
&& ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
|| TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"#"
......
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