Commit ddf36f4d authored by rsandifo's avatar rsandifo

gcc/

	PR target/60763
	* config/rs6000/vsx.md (vsx_xscvdpspn_scalar): Change input to DImode.
	* config/rs6000/rs6000.md (reload_vsx_from_gprsf): Update accordingly.
	Use gen_rtx_REG rather than simplify_gen_subreg for op0_di.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@209223 138bc75d-0d04-0410-961f-82ee72b054a4
parent a34c1231
2014-04-08 Richard Sandiford <rdsandiford@googlemail.com>
PR target/60763
* config/rs6000/vsx.md (vsx_xscvdpspn_scalar): Change input to DImode.
* config/rs6000/rs6000.md (reload_vsx_from_gprsf): Update accordingly.
Use gen_rtx_REG rather than simplify_gen_subreg for op0_di.
2014-04-08 Richard Biener <rguenther@suse.de>
PR middle-end/60706
......
......@@ -10029,13 +10029,16 @@
rtx op0 = operands[0];
rtx op1 = operands[1];
rtx op2 = operands[2];
rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0);
/* Also use the destination register to hold the unconverted DImode value.
This is conceptually a separate value from OP0, so we use gen_rtx_REG
rather than simplify_gen_subreg. */
rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
/* Move SF value to upper 32-bits for xscvspdpn. */
emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
emit_move_insn (op0_di, op2);
emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di));
DONE;
}
[(set_attr "length" "8")
......
......@@ -1223,7 +1223,7 @@
;; Used by direct move to move a SFmode value from GPR to VSX register
(define_insn "vsx_xscvspdpn_directmove"
[(set (match_operand:SF 0 "vsx_register_operand" "=wa")
(unspec:SF [(match_operand:SF 1 "vsx_register_operand" "wa")]
(unspec:SF [(match_operand:DI 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSPDPN))]
"TARGET_XSCVSPDPN"
"xscvspdpn %x0,%x1"
......
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