Commit 8e2b3539 authored by meissner's avatar meissner

[gcc]

2014-02-15  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/60203
	* config/rs6000/rs6000.md (rreg): Add TFmode, TDmode constraints.
	(mov<mode>_internal, TFmode/TDmode): Split TFmode/TDmode moves
	into 64-bit and 32-bit moves.  On 64-bit moves, add support for
	using direct move instructions on ISA 2.07.  Also adjust
	instruction length for 64-bit.
	(mov<mode>_64bit, TFmode/TDmode): Likewise.
	(mov<mode>_32bit, TFmode/TDmode): Likewise.

[gcc/testsuite]
2014-02-15  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/60203
	* gcc.target/powerpc/pr60203.c: New testsuite.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@207808 138bc75d-0d04-0410-961f-82ee72b054a4
parent 1f1c5345
2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/60203
* config/rs6000/rs6000.md (rreg): Add TFmode, TDmode constraints.
(mov<mode>_internal, TFmode/TDmode): Split TFmode/TDmode moves
into 64-bit and 32-bit moves. On 64-bit moves, add support for
using direct move instructions on ISA 2.07. Also adjust
instruction length for 64-bit.
(mov<mode>_64bit, TFmode/TDmode): Likewise.
(mov<mode>_32bit, TFmode/TDmode): Likewise.
2014-02-15 Alan Modra <amodra@gmail.com>
PR target/58675
......
......@@ -387,6 +387,8 @@
(define_mode_attr rreg [(SF "f")
(DF "ws")
(TF "f")
(TD "f")
(V4SF "wf")
(V2DF "wd")])
......@@ -9524,10 +9526,22 @@
;; It's important to list Y->r and r->Y before r->r because otherwise
;; reload, given m->r, will try to pick r->r and reload it, which
;; doesn't make progress.
(define_insn_and_split "*mov<mode>_internal"
(define_insn_and_split "*mov<mode>_64bit"
[(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")
(match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"#"
"&& reload_completed"
[(pc)]
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
[(set_attr "length" "8,8,8,12,12,8,8,8")])
(define_insn_and_split "*mov<mode>_32bit"
[(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
(match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
"TARGET_HARD_FLOAT && TARGET_FPRS
"TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"#"
......
2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/60203
* gcc.target/powerpc/pr60203.c: New testsuite.
2014-02-15 Mikael Morin <mikael@gcc.gnu.org>
PR fortran/59599
......
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-options "-mcpu=power8 -O3" } */
union u_ld { long double ld; double d[2]; };
long double
pack (double a, double aa)
{
union u_ld u;
u.d[0] = a;
u.d[1] = aa;
return u.ld;
}
double
unpack_0 (long double x)
{
union u_ld u;
u.ld = x;
return u.d[0];
}
double
unpack_1 (long double x)
{
union u_ld u;
u.ld = x;
return u.d[1];
}
/* { dg-final { scan-assembler-not "stfd" } } */
/* { dg-final { scan-assembler-not "lfd" } } */
/* { dg-final { scan-assembler-not "lxsdx" } } */
/* { dg-final { scan-assembler-not "stxsdx" } } */
/* { dg-final { scan-assembler-not "mfvsrd" } } */
/* { dg-final { scan-assembler-not "mtvsrd" } } */
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