Commit 579ee78b authored by meissner's avatar meissner

2014-08-12 Michael Meissner <meissner@linux.vnet.ibm.com>

	Backport patch from mainline
	2014-08-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/constraints.md (wh constraint): New constraint,
	for FP registers if direct move is available.
	(wi constraint): New constraint, for VSX/FP registers that can
	handle 64-bit integers.
	(wj constraint): New constraint for VSX/FP registers that can
	handle 64-bit integers for direct moves.
	(wk constraint): New constraint for VSX/FP registers that can
	handle 64-bit doubles for direct moves.
	(wy constraint): Make documentation match implementation.

	* config/rs6000/rs6000.c (struct rs6000_reg_addr): Add
	scalar_in_vmx_p field to simplify tests of whether SFmode or
	DFmode can go in the Altivec registers.
	(rs6000_hard_regno_mode_ok): Use scalar_in_vmx_p field.
	(rs6000_setup_reg_addr_masks): Likewise.
	(rs6000_debug_print_mode): Add debug support for scalar_in_vmx_p
	field, and wh/wi/wj/wk constraints.
	(rs6000_init_hard_regno_mode_ok): Setup scalar_in_vmx_p field, and
	the wh/wi/wj/wk constraints.
	(rs6000_preferred_reload_class): If SFmode/DFmode can go in the
	upper registers, prefer VSX registers unless the operation is a
	memory operation with REG+OFFSET addressing.

	* config/rs6000/vsx.md (VSr mode attribute): Add support for
	DImode.  Change SFmode to use ww constraint instead of d to allow
	SF registers in the upper registers.
	(VSr2): Likewise.
	(VSr3): Likewise.
	(VSr5): Fix thinko in comment.
	(VSa): New mode attribute that is an alternative to wa, that
	returns the VSX register class that a mode can go in, but may not
	be the preferred register class.
	(VS_64dm): New mode attribute for appropriate register classes for
	referencing 64-bit elements of vectors for direct moves and normal
	moves.
	(VS_64reg): Likewise.
	(vsx_mov<mode>): Change wa constraint to <VSa> to limit the
	register allocator to only registers the data type can handle.
	(vsx_le_perm_load_<mode>): Likewise.
	(vsx_le_perm_store_<mode>): Likewise.
	(vsx_xxpermdi2_le_<mode>): Likewise.
	(vsx_xxpermdi4_le_<mode>): Likewise.
	(vsx_lxvd2x2_le_<mode>): Likewise.
	(vsx_lxvd2x4_le_<mode>): Likewise.
	(vsx_stxvd2x2_le_<mode>): Likewise.
	(vsx_add<mode>3): Likewise.
	(vsx_sub<mode>3): Likewise.
	(vsx_mul<mode>3): Likewise.
	(vsx_div<mode>3): Likewise.
	(vsx_tdiv<mode>3_internal): Likewise.
	(vsx_fre<mode>2): Likewise.
	(vsx_neg<mode>2): Likewise.
	(vsx_abs<mode>2): Likewise.
	(vsx_nabs<mode>2): Likewise.
	(vsx_smax<mode>3): Likewise.
	(vsx_smin<mode>3): Likewise.
	(vsx_sqrt<mode>2): Likewise.
	(vsx_rsqrte<mode>2): Likewise.
	(vsx_tsqrt<mode>2_internal): Likewise.
	(vsx_fms<mode>4): Likewise.
	(vsx_nfma<mode>4): Likewise.
	(vsx_eq<mode>): Likewise.
	(vsx_gt<mode>): Likewise.
	(vsx_ge<mode>): Likewise.
	(vsx_eq<mode>_p): Likewise.
	(vsx_gt<mode>_p): Likewise.
	(vsx_ge<mode>_p): Likewise.
	(vsx_xxsel<mode>): Likewise.
	(vsx_xxsel<mode>_uns): Likewise.
	(vsx_copysign<mode>3): Likewise.
	(vsx_float<VSi><mode>2): Likewise.
	(vsx_floatuns<VSi><mode>2): Likewise.
	(vsx_fix_trunc<mode><VSi>2): Likewise.
	(vsx_fixuns_trunc<mode><VSi>2): Likewise.
	(vsx_x<VSv>r<VSs>i): Likewise.
	(vsx_x<VSv>r<VSs>ic): Likewise.
	(vsx_btrunc<mode>2): Likewise.
	(vsx_b2trunc<mode>2): Likewise.
	(vsx_floor<mode>2): Likewise.
	(vsx_ceil<mode>2): Likewise.
	(vsx_<VS_spdp_insn>): Likewise.
	(vsx_xscvspdp): Likewise.
	(vsx_xvcvspuxds): Likewise.
	(vsx_float_fix_<mode>2): Likewise.
	(vsx_set_<mode>): Likewise.
	(vsx_extract_<mode>_internal1): Likewise.
	(vsx_extract_<mode>_internal2): Likewise.
	(vsx_extract_<mode>_load): Likewise.
	(vsx_extract_<mode>_store): Likewise.
	(vsx_splat_<mode>): Likewise.
	(vsx_xxspltw_<mode>): Likewise.
	(vsx_xxspltw_<mode>_direct): Likewise.
	(vsx_xxmrghw_<mode>): Likewise.
	(vsx_xxmrglw_<mode>): Likewise.
	(vsx_xxsldwi_<mode>): Likewise.
	(vsx_xscvdpspn): Tighten constraints to only use register classes
	the types use.
	(vsx_xscvspdpn): Likewise.
	(vsx_xscvdpspn_scalar): Likewise.

	* config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wh, wi,
	wj, and wk constraints.
	(GPR_REG_CLASS_P): New helper macro for register classes targeting
	general purpose registers.

	* config/rs6000/rs6000.md (f32_dm): Use wh constraint for SDmode
	direct moves.
	(zero_extendsidi2_lfiwz): Use wj constraint for direct move of
	DImode instead of wm.  Use wk constraint for direct move of DFmode
	instead of wm.
	(extendsidi2_lfiwax): Likewise.
	(lfiwax): Likewise.
	(lfiwzx): Likewise.
	(movdi_internal64): Likewise.

	* doc/md.texi (PowerPC and IBM RS6000): Document wh, wi, wj, and
	wk constraints. Make the wy constraint documentation match them
	implementation.




git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_9-branch@213871 138bc75d-0d04-0410-961f-82ee72b054a4
parent c4d8418e
2014-08-12 Michael Meissner <meissner@linux.vnet.ibm.com>
Backport patch from mainline
2014-08-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/constraints.md (wh constraint): New constraint,
for FP registers if direct move is available.
(wi constraint): New constraint, for VSX/FP registers that can
handle 64-bit integers.
(wj constraint): New constraint for VSX/FP registers that can
handle 64-bit integers for direct moves.
(wk constraint): New constraint for VSX/FP registers that can
handle 64-bit doubles for direct moves.
(wy constraint): Make documentation match implementation.
* config/rs6000/rs6000.c (struct rs6000_reg_addr): Add
scalar_in_vmx_p field to simplify tests of whether SFmode or
DFmode can go in the Altivec registers.
(rs6000_hard_regno_mode_ok): Use scalar_in_vmx_p field.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_debug_print_mode): Add debug support for scalar_in_vmx_p
field, and wh/wi/wj/wk constraints.
(rs6000_init_hard_regno_mode_ok): Setup scalar_in_vmx_p field, and
the wh/wi/wj/wk constraints.
(rs6000_preferred_reload_class): If SFmode/DFmode can go in the
upper registers, prefer VSX registers unless the operation is a
memory operation with REG+OFFSET addressing.
* config/rs6000/vsx.md (VSr mode attribute): Add support for
DImode. Change SFmode to use ww constraint instead of d to allow
SF registers in the upper registers.
(VSr2): Likewise.
(VSr3): Likewise.
(VSr5): Fix thinko in comment.
(VSa): New mode attribute that is an alternative to wa, that
returns the VSX register class that a mode can go in, but may not
be the preferred register class.
(VS_64dm): New mode attribute for appropriate register classes for
referencing 64-bit elements of vectors for direct moves and normal
moves.
(VS_64reg): Likewise.
(vsx_mov<mode>): Change wa constraint to <VSa> to limit the
register allocator to only registers the data type can handle.
(vsx_le_perm_load_<mode>): Likewise.
(vsx_le_perm_store_<mode>): Likewise.
(vsx_xxpermdi2_le_<mode>): Likewise.
(vsx_xxpermdi4_le_<mode>): Likewise.
(vsx_lxvd2x2_le_<mode>): Likewise.
(vsx_lxvd2x4_le_<mode>): Likewise.
(vsx_stxvd2x2_le_<mode>): Likewise.
(vsx_add<mode>3): Likewise.
(vsx_sub<mode>3): Likewise.
(vsx_mul<mode>3): Likewise.
(vsx_div<mode>3): Likewise.
(vsx_tdiv<mode>3_internal): Likewise.
(vsx_fre<mode>2): Likewise.
(vsx_neg<mode>2): Likewise.
(vsx_abs<mode>2): Likewise.
(vsx_nabs<mode>2): Likewise.
(vsx_smax<mode>3): Likewise.
(vsx_smin<mode>3): Likewise.
(vsx_sqrt<mode>2): Likewise.
(vsx_rsqrte<mode>2): Likewise.
(vsx_tsqrt<mode>2_internal): Likewise.
(vsx_fms<mode>4): Likewise.
(vsx_nfma<mode>4): Likewise.
(vsx_eq<mode>): Likewise.
(vsx_gt<mode>): Likewise.
(vsx_ge<mode>): Likewise.
(vsx_eq<mode>_p): Likewise.
(vsx_gt<mode>_p): Likewise.
(vsx_ge<mode>_p): Likewise.
(vsx_xxsel<mode>): Likewise.
(vsx_xxsel<mode>_uns): Likewise.
(vsx_copysign<mode>3): Likewise.
(vsx_float<VSi><mode>2): Likewise.
(vsx_floatuns<VSi><mode>2): Likewise.
(vsx_fix_trunc<mode><VSi>2): Likewise.
(vsx_fixuns_trunc<mode><VSi>2): Likewise.
(vsx_x<VSv>r<VSs>i): Likewise.
(vsx_x<VSv>r<VSs>ic): Likewise.
(vsx_btrunc<mode>2): Likewise.
(vsx_b2trunc<mode>2): Likewise.
(vsx_floor<mode>2): Likewise.
(vsx_ceil<mode>2): Likewise.
(vsx_<VS_spdp_insn>): Likewise.
(vsx_xscvspdp): Likewise.
(vsx_xvcvspuxds): Likewise.
(vsx_float_fix_<mode>2): Likewise.
(vsx_set_<mode>): Likewise.
(vsx_extract_<mode>_internal1): Likewise.
(vsx_extract_<mode>_internal2): Likewise.
(vsx_extract_<mode>_load): Likewise.
(vsx_extract_<mode>_store): Likewise.
(vsx_splat_<mode>): Likewise.
(vsx_xxspltw_<mode>): Likewise.
(vsx_xxspltw_<mode>_direct): Likewise.
(vsx_xxmrghw_<mode>): Likewise.
(vsx_xxmrglw_<mode>): Likewise.
(vsx_xxsldwi_<mode>): Likewise.
(vsx_xscvdpspn): Tighten constraints to only use register classes
the types use.
(vsx_xscvspdpn): Likewise.
(vsx_xscvdpspn_scalar): Likewise.
* config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wh, wi,
wj, and wk constraints.
(GPR_REG_CLASS_P): New helper macro for register classes targeting
general purpose registers.
* config/rs6000/rs6000.md (f32_dm): Use wh constraint for SDmode
direct moves.
(zero_extendsidi2_lfiwz): Use wj constraint for direct move of
DImode instead of wm. Use wk constraint for direct move of DFmode
instead of wm.
(extendsidi2_lfiwax): Likewise.
(lfiwax): Likewise.
(lfiwzx): Likewise.
(movdi_internal64): Likewise.
* doc/md.texi (PowerPC and IBM RS6000): Document wh, wi, wj, and
wk constraints. Make the wy constraint documentation match them
implementation.
2014-08-12 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
Backport from mainline
......
......@@ -68,6 +68,20 @@
(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"
"If -mmfpgpr was used, a floating point register or NO_REGS.")
(define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]"
"Floating point register if direct moves are available, or NO_REGS.")
;; At present, DImode is not allowed in the Altivec registers. If in the
;; future it is allowed, wi/wj can be set to VSX_REGS instead of FLOAT_REGS.
(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
"FP or VSX register to hold 64-bit integers or NO_REGS.")
(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]"
"FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.")
(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]"
"FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.")
(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]"
"Floating point register if the LFIWAX instruction is enabled or NO_REGS.")
......@@ -101,7 +115,7 @@
"Floating point register if the STFIWX instruction is enabled or NO_REGS.")
(define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]"
"VSX vector register to hold scalar float values or NO_REGS.")
"FP or VSX register to perform ISA 2.07 float ops or NO_REGS.")
(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"
"Floating point register if the LFIWZX instruction is enabled or NO_REGS.")
......
This diff is collapsed.
......@@ -1478,6 +1478,10 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */
RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */
RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */
RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */
RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */
RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */
RS6000_CONSTRAINT_wm, /* VSX register for direct move */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
......@@ -1502,6 +1506,9 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
#define VSX_REG_CLASS_P(CLASS) \
((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
/* Return whether a given register class targets general purpose registers. */
#define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.
In general this is just CLASS; but on some machines
......
......@@ -328,7 +328,7 @@
(define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
; Definitions for 32-bit fpr direct move
(define_mode_attr f32_dm [(SF "wn") (SD "wm")])
(define_mode_attr f32_dm [(SF "wn") (SD "wh")])
; These modes do not fit in integer registers in 32-bit mode.
; but on e500v2, the gpr are 64 bit registers
......@@ -577,7 +577,7 @@
"")
(define_insn "*zero_extendsidi2_lfiwzx"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu")
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
(zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
"TARGET_POWERPC64 && TARGET_LFIWZX"
"@
......@@ -747,7 +747,7 @@
"")
(define_insn "*extendsidi2_lfiwax"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu")
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
(sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
"TARGET_POWERPC64 && TARGET_LFIWAX"
"@
......@@ -5625,7 +5625,7 @@
; We don't define lfiwax/lfiwzx with the normal definition, because we
; don't want to support putting SImode in FPR registers.
(define_insn "lfiwax"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,!wj")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
UNSPEC_LFIWAX))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
......@@ -5705,7 +5705,7 @@
(set_attr "type" "fpload")])
(define_insn "lfiwzx"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,!wj")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
UNSPEC_LFIWZX))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
......@@ -9459,8 +9459,8 @@
; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload.
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm")
(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))]
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wk")
(match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wk,r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
......@@ -10239,8 +10239,8 @@
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm,?*wm")
(match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r,O"))]
[(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi")
(match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))]
"TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
......
This diff is collapsed.
......@@ -2126,6 +2126,18 @@ VSX vector register to hold vector float data or NO_REGS.
@item wg
If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
@item wh
Floating point register if direct moves are available, or NO_REGS.
@item wi
FP or VSX register to hold 64-bit integers or NO_REGS.
@item wj
FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
@item wk
FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
@item wl
Floating point register if the LFIWAX instruction is enabled or NO_REGS.
......@@ -2157,7 +2169,7 @@ FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
Floating point register if the STFIWX instruction is enabled or NO_REGS.
@item wy
VSX vector register to hold scalar float values or NO_REGS.
FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
@item wz
Floating point register if the LFIWZX instruction is enabled or NO_REGS.
......
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