Commit 49f88007 authored by Doug Gilbert's avatar Doug Gilbert

Indicate that PPE42 fused branch instructions modify the CR

parent ffd86801
...@@ -19172,12 +19172,19 @@ rs6000_emit_cbranch (enum machine_mode mode, rtx operands[]) ...@@ -19172,12 +19172,19 @@ rs6000_emit_cbranch (enum machine_mode mode, rtx operands[])
} }
else // Use the PPE fused compare-branch instructions else // Use the PPE fused compare-branch instructions
{ {
emit_jump_insn(gen_rtx_SET(VOIDmode, rtx cc_clobber = gen_rtx_CLOBBER (CCmode, gen_rtx_REG(CCmode,CR0_REGNO));
pc_rtx, emit_jump_insn
gen_rtx_IF_THEN_ELSE(VOIDmode, ( gen_rtx_PARALLEL
operands[0], (VOIDmode,
loc_ref, gen_rtvec(2,
pc_rtx))); gen_rtx_SET(VOIDmode,
pc_rtx,
gen_rtx_IF_THEN_ELSE(VOIDmode,
operands[0],
loc_ref,
pc_rtx)),
cc_clobber))
);
} }
} }
...@@ -19188,7 +19195,7 @@ rs6000_emit_cbranch (enum machine_mode mode, rtx operands[]) ...@@ -19188,7 +19195,7 @@ rs6000_emit_cbranch (enum machine_mode mode, rtx operands[])
OP is the conditional expression. XEXP (OP, 0) is assumed to be a OP is the conditional expression. XEXP (OP, 0) is assumed to be a
condition code register and its mode specifies what kind of condition code register and its mode specifies what kind of
comparison we made. comparison is being done.
REVERSED is nonzero if we should reverse the sense of the comparison. REVERSED is nonzero if we should reverse the sense of the comparison.
...@@ -19208,7 +19215,7 @@ output_fused_cbranch (rtx operands[], const char *label, rtx insn) ...@@ -19208,7 +19215,7 @@ output_fused_cbranch (rtx operands[], const char *label, rtx insn)
if(need_longbranch) if(need_longbranch)
code = reverse_condition (code); code = reverse_condition (code);
switch (code) switch (code)
{ {
case NE: case NE:
...@@ -19260,7 +19267,7 @@ output_fused_cbranch (rtx operands[], const char *label, rtx insn) ...@@ -19260,7 +19267,7 @@ output_fused_cbranch (rtx operands[], const char *label, rtx insn)
s += sprintf(s, "cmp%sw%sb%s %d, %d", logical, s += sprintf(s, "cmp%sw%sb%s %d, %d", logical,
immed, ccode, REGNO(operands[2]), op3); immed, ccode, REGNO(operands[2]), op3);
if (need_longbranch) if (need_longbranch)
s += sprintf(s, ",$+8\n\tb %s", label); s += sprintf(s, ",$+8\n\tb %s", label);
else else
...@@ -19282,7 +19289,7 @@ output_fused_bnbwi(rtx operands[], const char *label, bool longbranch) ...@@ -19282,7 +19289,7 @@ output_fused_bnbwi(rtx operands[], const char *label, bool longbranch)
if(longbranch) if(longbranch)
code = reverse_condition (code); code = reverse_condition (code);
switch (code) switch (code)
{ {
case NE: // not eq zero so it's 1 case NE: // not eq zero so it's 1
...@@ -19299,7 +19306,7 @@ output_fused_bnbwi(rtx operands[], const char *label, bool longbranch) ...@@ -19299,7 +19306,7 @@ output_fused_bnbwi(rtx operands[], const char *label, bool longbranch)
bit_value, bit_value,
regno, regno,
bitpos); bitpos);
if (longbranch) if (longbranch)
s += sprintf(s, ",$+8\n\tb %s", label); s += sprintf(s, ",$+8\n\tb %s", label);
else else
......
...@@ -14930,7 +14930,8 @@ ...@@ -14930,7 +14930,8 @@
(match_operand:SI 3 "const_int_operand" "")) (match_operand:SI 3 "const_int_operand" ""))
(const_int 0)]) (const_int 0)])
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0 "" ""))
(pc)))] (pc)))
(clobber (reg:CC CR0_REGNO))]
"(rs6000_cpu == PROCESSOR_PPE42) && optimize_size" "(rs6000_cpu == PROCESSOR_PPE42) && optimize_size"
"* "*
{ {
...@@ -14946,7 +14947,8 @@ ...@@ -14946,7 +14947,8 @@
(match_operand:SI 3 "exact_log2_inverted_cint_operand" "n")) (match_operand:SI 3 "exact_log2_inverted_cint_operand" "n"))
(const_int 0)]) (const_int 0)])
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0 "" ""))
(pc)))] (pc)))
(clobber (reg:CC CR0_REGNO))]
"(rs6000_cpu == PROCESSOR_PPE42) && optimize_size" "(rs6000_cpu == PROCESSOR_PPE42) && optimize_size"
"* "*
{ {
...@@ -14969,7 +14971,8 @@ ...@@ -14969,7 +14971,8 @@
[(match_operand:GPR 2 "gpc_reg_operand" "r") [(match_operand:GPR 2 "gpc_reg_operand" "r")
(match_operand:GPR 3 "gpc_reg_operand" "r")]) (match_operand:GPR 3 "gpc_reg_operand" "r")])
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0 "" ""))
(pc)))] (pc)))
(clobber (reg:CC CR0_REGNO))]
"(rs6000_cpu == PROCESSOR_PPE42) && optimize_size" "(rs6000_cpu == PROCESSOR_PPE42) && optimize_size"
"* "*
{ {
...@@ -14982,12 +14985,13 @@ ...@@ -14982,12 +14985,13 @@
;; illegal immediaate values ;; illegal immediaate values
(define_insn "*cmpwib" (define_insn "*cmpwib"
[(set (pc) [(set (pc)
(if_then_else (match_operator 1 "rs6000_fused_cbranch_operator" (if_then_else (match_operator 1 "rs6000_fused_cbranch_operator"
[(match_operand:GPR 2 "gpc_reg_operand" "r") [(match_operand:GPR 2 "gpc_reg_operand" "r")
(match_operand:SI 3 "u5bit_cint_operand" "I")]) (match_operand:SI 3 "u5bit_cint_operand" "I")])
(label_ref (match_operand 0 "" "")) (label_ref (match_operand 0 "" ""))
(pc)))] (pc)))
(clobber (reg:CC CR0_REGNO))]
"(rs6000_cpu == PROCESSOR_PPE42) && optimize_size" "(rs6000_cpu == PROCESSOR_PPE42) && optimize_size"
"* "*
{ {
......
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