Commit 2f2eb785 authored by Doug Gilbert's avatar Doug Gilbert Committed by Patrick Williams

Turn off 64bit load/stores in epilog/proglog

parent 60db5f9d
......@@ -23475,7 +23475,7 @@ rs6000_emit_prologue (void)
if ((strategy & SAVE_INLINE_GPRS))
{
// ppe42 - use 64 bit stores - No evidence that this gained anything
if(rs6000_cpu == PROCESSOR_PPE42)
if(rs6000_cpu == PROCESSOR_TITAN) // TODO disable for now PROCESSOR_PPE42)
{
i = 0;
if((info->first_gp_reg_save & 0x01) == 1) // odd reg num
......@@ -23589,7 +23589,7 @@ rs6000_emit_prologue (void)
int i;
// ppe42 save using 64-bit stores
if(rs6000_cpu == PROCESSOR_PPE42)
if(rs6000_cpu == PROCESSOR_TITAN) // TODO disable for now PROCESSOR_PPE42)
{
i = 0;
if((info->first_gp_reg_save & 0x1) == 1) // odd regnum
......@@ -25046,7 +25046,7 @@ rs6000_emit_epilogue (int sibcall)
else
{
// ppe42 - use 64 bit loads
if(rs6000_cpu == PROCESSOR_PPE42)
if(rs6000_cpu == PROCESSOR_TITAN) // TODO turn off PROCESSOR_PPE42)
{
i = 0;
if((info->first_gp_reg_save & 0x1) == 1) // odd reg
......
......@@ -892,6 +892,8 @@
(const_string "load_u")
(const_string "*")))])])
;; FIXME this insn has a length problem - needs to be split
;; one when two instructions are used the set_addr "length" "8"
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m")))]
......@@ -10279,7 +10281,7 @@
"@
stvd%U0%X0 %1, %0
lvd%U1%X1 %0, %1
# movedi_internal32 %0, %1 FIXME
# movedi_internal32 %0, %1 REPORT ME!
stfd%U0%X0 %1,%0
lfd%U1%X1 %0,%1
fmr %0,%1
......
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