Commit 0c6c36e8 authored by Doug Gilbert's avatar Doug Gilbert Committed by Patrick Williams

PPE42 compiler generates invalid crnot instruction

parent 2f2eb785
...@@ -13088,12 +13088,16 @@ ...@@ -13088,12 +13088,16 @@
DONE; DONE;
}") }")
/* PPE42 does not support asm instructions to directly
manipulate the condition register (aka crnot, crxor etc. )
so don't support cstore on PPE42 */
(define_expand "cstore<mode>4" (define_expand "cstore<mode>4"
[(use (match_operator 1 "rs6000_cbranch_operator" [(use (match_operator 1 "rs6000_cbranch_operator"
[(match_operand:GPR 2 "gpc_reg_operand" "") [(match_operand:GPR 2 "gpc_reg_operand" "")
(match_operand:GPR 3 "reg_or_short_operand" "")])) (match_operand:GPR 3 "reg_or_short_operand" "")]))
(clobber (match_operand:SI 0 "register_operand"))] (clobber (match_operand:SI 0 "register_operand"))]
"" "rs6000_cpu != PROCESSOR_PPE42"
" "
{ {
/* Take care of the possibility that operands[3] might be negative but /* Take care of the possibility that operands[3] might be negative but
...@@ -13128,7 +13132,7 @@ ...@@ -13128,7 +13132,7 @@
[(match_operand:FP 2 "gpc_reg_operand" "") [(match_operand:FP 2 "gpc_reg_operand" "")
(match_operand:FP 3 "gpc_reg_operand" "")])) (match_operand:FP 3 "gpc_reg_operand" "")]))
(clobber (match_operand:SI 0 "register_operand"))] (clobber (match_operand:SI 0 "register_operand"))]
"" "rs6000_cpu != PROCESSOR_PPE42"
" "
{ {
rs6000_emit_sCOND (<MODE>mode, operands); rs6000_emit_sCOND (<MODE>mode, operands);
......
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