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;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
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;; Copyright (C) 1990-2014 Free Software Foundation, Inc.
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;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.
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;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
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;;
;; REGNOS
;;

(define_constants
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  [(FIRST_GPR_REGNO		0)
   (STACK_POINTER_REGNUM	1)
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   (TOC_REGNUM			2)
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   (STATIC_CHAIN_REGNUM		10)
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   (HARD_FRAME_POINTER_REGNUM	31)
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   (LAST_GPR_REGNO		31)
   (FIRST_FPR_REGNO		32)
   (LAST_FPR_REGNO		63)
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   (LR_REGNO			65)
   (CTR_REGNO			66)
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   (ARG_POINTER_REGNUM		67)
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   (CR0_REGNO			68)
   (CR1_REGNO			69)
   (CR2_REGNO			70)
   (CR3_REGNO			71)
   (CR4_REGNO			72)
   (CR5_REGNO			73)
   (CR6_REGNO			74)
   (CR7_REGNO			75)
   (MAX_CR_REGNO		75)
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   (CA_REGNO			76)
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   (FIRST_ALTIVEC_REGNO		77)
   (LAST_ALTIVEC_REGNO		108)
   (VRSAVE_REGNO		109)
   (VSCR_REGNO			110)
   (SPE_ACC_REGNO		111)
   (SPEFSCR_REGNO		112)
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   (FRAME_POINTER_REGNUM	113)
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   (TFHAR_REGNO			114)
   (TFIAR_REGNO			115)
   (TEXASR_REGNO		116)
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   (FIRST_SPE_HIGH_REGNO	117)
   (LAST_SPE_HIGH_REGNO		148)
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  ])

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;;
;; UNSPEC usage
;;

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(define_c_enum "unspec"
  [UNSPEC_FRSP			; frsp for POWER machines
   UNSPEC_PROBE_STACK		; probe stack memory reference
   UNSPEC_TOCPTR		; address of a word pointing to the TOC
   UNSPEC_TOC			; address of the TOC (more-or-less)
   UNSPEC_MOVSI_GOT
   UNSPEC_MV_CR_OV		; move_from_CR_ov_bit
   UNSPEC_FCTIWZ
   UNSPEC_FRIM
   UNSPEC_FRIN
   UNSPEC_FRIP
   UNSPEC_FRIZ
   UNSPEC_LD_MPIC		; load_macho_picbase
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   UNSPEC_RELD_MPIC		; re-load_macho_picbase
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   UNSPEC_MPIC_CORRECT		; macho_correct_pic
   UNSPEC_TLSGD
   UNSPEC_TLSLD
   UNSPEC_MOVESI_FROM_CR
   UNSPEC_MOVESI_TO_CR
   UNSPEC_TLSDTPREL
   UNSPEC_TLSDTPRELHA
   UNSPEC_TLSDTPRELLO
   UNSPEC_TLSGOTDTPREL
   UNSPEC_TLSTPREL
   UNSPEC_TLSTPRELHA
   UNSPEC_TLSTPRELLO
   UNSPEC_TLSGOTTPREL
   UNSPEC_TLSTLS
   UNSPEC_FIX_TRUNC_TF		; fadd, rounding towards zero
   UNSPEC_MV_CR_GT		; move_from_CR_gt_bit
   UNSPEC_STFIWX
   UNSPEC_POPCNTB
   UNSPEC_FRES
   UNSPEC_SP_SET
   UNSPEC_SP_TEST
   UNSPEC_SYNC
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   UNSPEC_LWSYNC
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   UNSPEC_SYNC_OP
   UNSPEC_ATOMIC
   UNSPEC_CMPXCHG
   UNSPEC_XCHG
   UNSPEC_AND
   UNSPEC_DLMZB
   UNSPEC_DLMZB_CR
   UNSPEC_DLMZB_STRLEN
   UNSPEC_RSQRT
   UNSPEC_TOCREL
   UNSPEC_MACHOPIC_OFFSET
   UNSPEC_BPERM
   UNSPEC_COPYSIGN
   UNSPEC_PARITY
   UNSPEC_FCTIW
   UNSPEC_FCTID
   UNSPEC_LFIWAX
   UNSPEC_LFIWZX
   UNSPEC_FCTIWUZ
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   UNSPEC_GRP_END_NOP
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   UNSPEC_P8V_FMRGOW
   UNSPEC_P8V_MTVSRWZ
   UNSPEC_P8V_RELOAD_FROM_GPR
   UNSPEC_P8V_MTVSRD
   UNSPEC_P8V_XXPERMDI
   UNSPEC_P8V_RELOAD_FROM_VSX
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   UNSPEC_ADDG6S
   UNSPEC_CDTBCD
   UNSPEC_CBCDTD
   UNSPEC_DIVE
   UNSPEC_DIVEO
   UNSPEC_DIVEU
   UNSPEC_DIVEUO
   UNSPEC_UNPACK_128BIT
   UNSPEC_PACK_128BIT
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   UNSPEC_LSQ
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   UNSPEC_FUSION_GPR
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  ])

;;
;; UNSPEC_VOLATILE usage
;;

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(define_c_enum "unspecv"
  [UNSPECV_BLOCK
   UNSPECV_LL			; load-locked
   UNSPECV_SC			; store-conditional
   UNSPECV_PROBE_STACK_RANGE	; probe range of stack addresses
   UNSPECV_EH_RR		; eh_reg_restore
   UNSPECV_ISYNC		; isync instruction
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   UNSPECV_MFTB			; move from time base
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   UNSPECV_NLGR			; non-local goto receiver
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   UNSPECV_MFFS			; Move from FPSCR
   UNSPECV_MTFSF		; Move to FPSCR Fields
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  ])
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;; Define an insn type attribute.  This is used in function unit delay
;; computations.
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(define_attr "type"
"integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,fused_branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto,htm"
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  (const_string "integer"))

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;; Define floating point instruction sub-types for use with Xfpu.md
(define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))

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;; Length (in bytes).
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; '(pc)' in the following doesn't include the instruction itself; it is
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; calculated as if the instruction had zero size.
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(define_attr "length" ""
  (if_then_else (eq_attr "type" "branch")
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		(if_then_else (and (ge (minus (match_dup 0) (pc))
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				       (const_int -32768))
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				   (lt (minus (match_dup 0) (pc))
				       (const_int 32764)))
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			      (const_int 4)
			      (const_int 8))
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        (if_then_else (eq_attr "type" "fused_branch")
            (if_then_else (and (ge(minus (match_dup 0) (pc))
                           (const_int -2048))
                        (lt (minus (match_dup 0) (pc))
                            (const_int 2044)))
                        (const_int 4)
                        (const_int 8))
		(const_int 4))))
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;; Processor type -- this attribute must exactly match the processor_type
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;; enumeration in rs6000-opts.h.
(define_attr "cpu"
  "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
   ppc750,ppc7400,ppc7450,
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   ppc403,ppc405,ppe405,ppe42,ppc440,ppc476,
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   ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
   power4,power5,power6,power7,power8,
   rs64a,mpccore,cell,ppca2,titan"
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  (const (symbol_ref "rs6000_cpu_attr")))

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;; If this instruction is microcoded on the CELL processor
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; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
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(define_attr "cell_micro" "not,conditional,always"
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  (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
		(const_string "always")
		(const_string "not")))
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(automata_option "ndfa")

(include "rs64.md")
(include "mpc.md")
(include "40x.md")
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(include "440.md")
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(include "476.md")
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(include "601.md")
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(include "603.md")
(include "6xx.md")
(include "7xx.md")
(include "7450.md")
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(include "8540.md")
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(include "e300c2c3.md")
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(include "e500mc.md")
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(include "e500mc64.md")
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(include "e5500.md")
(include "e6500.md")
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(include "power4.md")
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(include "power5.md")
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(include "power6.md")
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(include "power7.md")
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(include "power8.md")
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(include "cell.md")
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(include "xfpu.md")
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(include "a2.md")
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(include "titan.md")
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(include "predicates.md")
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(include "constraints.md")
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(include "darwin.md")
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242

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;; Mode iterators
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; This mode iterator allows :GPR to be used to indicate the allowable size
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; of whole values in GPRs.
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(define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
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; Any supported integer mode.
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(define_mode_iterator INT [QI HI SI DI TI PTI])
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; Any supported integer mode that fits in one register.
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(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
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; extend modes for DImode
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(define_mode_iterator QHSI [QI HI SI])
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; QImode or HImode for small atomic ops
(define_mode_iterator QHI [QI HI])

; HImode or SImode for sign extended fusion ops
(define_mode_iterator HSI [HI SI])

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; SImode or DImode, even if DImode doesn't fit in GPRs.
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(define_mode_iterator SDI [SI DI])
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; The size of a pointer.  Also, the size of the value that a record-condition
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; (one with a '.') will compare; and the size used for arithmetic carries.
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(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
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; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
; PTImode is GPR only)
(define_mode_iterator TI2 [TI PTI])

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; Any hardware-supported floating-point mode
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(define_mode_iterator FP [
  (SF "TARGET_HARD_FLOAT 
   && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
  (DF "TARGET_HARD_FLOAT 
   && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
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  (TF "!TARGET_IEEEQUAD
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   && TARGET_HARD_FLOAT
   && (TARGET_FPRS || TARGET_E500_DOUBLE)
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   && TARGET_LONG_DOUBLE_128")
  (DD "TARGET_DFP")
  (TD "TARGET_DFP")])
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; Any fma capable floating-point mode.
(define_mode_iterator FMA_F [
  (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
  (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
       || VECTOR_UNIT_VSX_P (DFmode)")
  (V2SF "TARGET_PAIRED_FLOAT")
  (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
  (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
  ])

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; Floating point move iterators to combine binary and decimal moves
(define_mode_iterator FMOVE32 [SF SD])
(define_mode_iterator FMOVE64 [DF DD])
(define_mode_iterator FMOVE64X [DI DF DD])
(define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
				(TD "TARGET_HARD_FLOAT && TARGET_FPRS")])

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; Iterators for 128 bit types for direct move
(define_mode_iterator FMOVE128_GPR [(TI    "TARGET_VSX_TIMODE")
				    (V16QI "")
				    (V8HI  "")
				    (V4SI  "")
				    (V4SF  "")
				    (V2DI  "")
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				    (V2DF  "")
				    (V1TI  "")])
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; Whether a floating point move is ok, don't allow SD without hardware FP
(define_mode_attr fmove_ok [(SF "")
			    (DF "")
			    (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
			    (DD "")])

; Convert REAL_VALUE to the appropriate bits
(define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
					(DF "REAL_VALUE_TO_TARGET_DOUBLE")
					(SD "REAL_VALUE_TO_TARGET_DECIMAL32")
					(DD "REAL_VALUE_TO_TARGET_DECIMAL64")])

; Definitions for load to 32-bit fpr register
(define_mode_attr f32_lr [(SF "f")		 (SD "wz")])
(define_mode_attr f32_lm [(SF "m")		 (SD "Z")])
(define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
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(define_mode_attr f32_lv [(SF "lxsspx %x0,%y1")	 (SD "lxsiwzx %x0,%y1")])
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; Definitions for store from 32-bit fpr register
(define_mode_attr f32_sr [(SF "f")		  (SD "wx")])
(define_mode_attr f32_sm [(SF "m")		  (SD "Z")])
(define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
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(define_mode_attr f32_sv [(SF "stxsspx %x1,%y0")  (SD "stxsiwzx %x1,%y0")])
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; Definitions for 32-bit fpr direct move
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; At present, the decimal modes are not allowed in the traditional altivec
; registers, so restrict the constraints to just the traditional FPRs.
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(define_mode_attr f32_dm [(SF "wn") (SD "wh")])
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; Definitions for 32-bit VSX
(define_mode_attr f32_vsx [(SF "ww") (SD "wn")])

; Definitions for 32-bit use of altivec registers
(define_mode_attr f32_av  [(SF "wu") (SD "wn")])

; Definitions for 64-bit VSX
(define_mode_attr f64_vsx [(DF "ws") (DD "wn")])

; Definitions for 64-bit direct move
(define_mode_attr f64_dm  [(DF "wk") (DD "wh")])

; Definitions for 64-bit use of altivec registers
(define_mode_attr f64_av  [(DF "wv") (DD "wn")])

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; These modes do not fit in integer registers in 32-bit mode.
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; but on e500v2, the gpr are 64 bit registers
(define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
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; Iterator for reciprocal estimate instructions
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(define_mode_iterator RECIPF [SF DF V4SF V2DF])

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; Iterator for just SF/DF
(define_mode_iterator SFDF [SF DF])

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; SF/DF suffix for traditional floating instructions
(define_mode_attr Ftrad		[(SF "s") (DF "")])

; SF/DF suffix for VSX instructions
(define_mode_attr Fvsx		[(SF "sp") (DF	"dp")])

; SF/DF constraint for arithmetic on traditional floating point registers
(define_mode_attr Ff		[(SF "f") (DF "d")])

; SF/DF constraint for arithmetic on VSX registers
(define_mode_attr Fv		[(SF "wy") (DF "ws")])

; s/d suffix for things like fp_addsub_s/fp_addsub_d
(define_mode_attr Fs		[(SF "s")  (DF "d")])

; FRE/FRES support
(define_mode_attr Ffre		[(SF "fres") (DF "fre")])
(define_mode_attr FFRE		[(SF "FRES") (DF "FRE")])

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; Conditional returns.
(define_code_iterator any_return [return simple_return])
(define_code_attr return_pred [(return "direct_return ()")
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			       (simple_return "1")])
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(define_code_attr return_str [(return "") (simple_return "simple_")])

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; Various instructions that come in SI and DI forms.
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; A generic w/d attribute, for things like cmpw/cmpd.
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(define_mode_attr wd [(QI    "b")
		      (HI    "h")
		      (SI    "w")
		      (DI    "d")
		      (V16QI "b")
		      (V8HI  "h")
		      (V4SI  "w")
		      (V2DI  "d")])
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; DImode bits
(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
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;; ISEL/ISEL64 target selection
(define_mode_attr sel [(SI "") (DI "64")])

;; Suffix for reload patterns
(define_mode_attr ptrsize [(SI "32bit")
			   (DI "64bit")])

(define_mode_attr tptrsize [(SI "TARGET_32BIT")
			    (DI "TARGET_64BIT")])

(define_mode_attr mptrsize [(SI "si")
			    (DI "di")])

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(define_mode_attr ptrload [(SI "lwz")
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			   (DI "ld")])

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(define_mode_attr ptrm [(SI "m")
			(DI "Y")])

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(define_mode_attr rreg [(SF   "f")
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			(DF   "ws")
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			(TF   "f")
			(TD   "f")
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			(V4SF "wf")
			(V2DF "wd")])
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(define_mode_attr rreg2 [(SF   "f")
			 (DF   "d")])

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(define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
				 (DF "TARGET_FCFID")])

(define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
				(DF "TARGET_E500_DOUBLE")])

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(define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
				(DF "TARGET_DOUBLE_FLOAT")])
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;; Mode iterator for logical operations on 128-bit types
(define_mode_iterator BOOL_128		[TI
					 PTI
					 (V16QI	"TARGET_ALTIVEC")
					 (V8HI	"TARGET_ALTIVEC")
					 (V4SI	"TARGET_ALTIVEC")
					 (V4SF	"TARGET_ALTIVEC")
					 (V2DI	"TARGET_ALTIVEC")
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					 (V2DF	"TARGET_ALTIVEC")
					 (V1TI  "TARGET_ALTIVEC")])
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;; For the GPRs we use 3 constraints for register outputs, two that are the
;; same as the output register, and a third where the output register is an
;; early clobber, so we don't have to deal with register overlaps.  For the
;; vector types, we prefer to use the vector registers.  For TI mode, allow
;; either.

;; Mode attribute for boolean operation register constraints for output
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(define_mode_attr BOOL_REGS_OUTPUT	[(TI	"&r,r,r,wt,v")
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					 (PTI	"&r,r,r")
					 (V16QI	"wa,v,&?r,?r,?r")
					 (V8HI	"wa,v,&?r,?r,?r")
					 (V4SI	"wa,v,&?r,?r,?r")
					 (V4SF	"wa,v,&?r,?r,?r")
					 (V2DI	"wa,v,&?r,?r,?r")
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					 (V2DF	"wa,v,&?r,?r,?r")
					 (V1TI	"wa,v,&?r,?r,?r")])
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;; Mode attribute for boolean operation register constraints for operand1
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(define_mode_attr BOOL_REGS_OP1		[(TI	"r,0,r,wt,v")
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					 (PTI	"r,0,r")
					 (V16QI	"wa,v,r,0,r")
					 (V8HI	"wa,v,r,0,r")
					 (V4SI	"wa,v,r,0,r")
					 (V4SF	"wa,v,r,0,r")
					 (V2DI	"wa,v,r,0,r")
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					 (V2DF	"wa,v,r,0,r")
					 (V1TI	"wa,v,r,0,r")])
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;; Mode attribute for boolean operation register constraints for operand2
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(define_mode_attr BOOL_REGS_OP2		[(TI	"r,r,0,wt,v")
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					 (PTI	"r,r,0")
					 (V16QI	"wa,v,r,r,0")
					 (V8HI	"wa,v,r,r,0")
					 (V4SI	"wa,v,r,r,0")
					 (V4SF	"wa,v,r,r,0")
					 (V2DI	"wa,v,r,r,0")
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					 (V2DF	"wa,v,r,r,0")
					 (V1TI	"wa,v,r,r,0")])
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;; Mode attribute for boolean operation register constraints for operand1
;; for one_cmpl.  To simplify things, we repeat the constraint where 0
;; is used for operand1 or operand2
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(define_mode_attr BOOL_REGS_UNARY	[(TI	"r,0,0,wt,v")
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					 (PTI	"r,0,0")
					 (V16QI	"wa,v,r,0,0")
					 (V8HI	"wa,v,r,0,0")
					 (V4SI	"wa,v,r,0,0")
					 (V4SF	"wa,v,r,0,0")
					 (V2DI	"wa,v,r,0,0")
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					 (V2DF	"wa,v,r,0,0")
					 (V1TI	"wa,v,r,0,0")])
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;; Mode attribute for the clobber of CC0 for AND expansion.
;; For the 128-bit types, we never do AND immediate, but we need to
;; get the correct number of X's for the number of operands.
(define_mode_attr BOOL_REGS_AND_CR0	[(TI	"X,X,X,X,X")
					 (PTI	"X,X,X")
					 (V16QI	"X,X,X,X,X")
					 (V8HI	"X,X,X,X,X")
					 (V4SI	"X,X,X,X,X")
					 (V4SF	"X,X,X,X,X")
					 (V2DI	"X,X,X,X,X")
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					 (V2DF	"X,X,X,X,X")
					 (V1TI	"X,X,X,X,X")])
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;; Mode attribute to give the correct type for integer divides
(define_mode_attr idiv_ldiv [(SI "idiv")
			     (DI "ldiv")])

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526

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;; Start with fixed-point load and store insns.  Here we put only the more
;; complex forms.  Basic data transfer is done later.

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(define_expand "zero_extend<mode>di2"
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  [(set (match_operand:DI 0 "gpc_reg_operand" "")
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	(zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
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  "TARGET_POWERPC64"
  "")

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(define_insn "*zero_extend<mode>di2_internal1"
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  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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	(zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
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  "TARGET_POWERPC64 && (<MODE>mode != SImode || !TARGET_LFIWZX)"
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  "@
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   l<wd>z%U1%X1 %0,%1
   rldicl %0,%1,0,<dbits>"
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  [(set_attr_alternative "type"
      [(if_then_else
	 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
	 (const_string "load_ux")
	 (if_then_else
	   (match_test "update_address_mem (operands[1], VOIDmode)")
	   (const_string "load_u")
	   (const_string "load")))
       (const_string "*")])])
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(define_insn "*zero_extend<mode>di2_internal2"
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  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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	(compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
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   (clobber (match_scratch:DI 2 "=r,r"))]
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  "TARGET_64BIT"
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  "@
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   rldicl. %2,%1,0,<dbits>
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   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
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  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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	(compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
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		    (const_int 0)))
   (clobber (match_scratch:DI 2 ""))]
  "TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 2)
	(zero_extend:DI (match_dup 1)))
   (set (match_dup 0)
	(compare:CC (match_dup 2)
		    (const_int 0)))]
  "")
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(define_insn "*zero_extend<mode>di2_internal3"
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  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
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	(compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
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   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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	(zero_extend:DI (match_dup 1)))]
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  "TARGET_64BIT"
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  "@
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   rldicl. %0,%1,0,<dbits>
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   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
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  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
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	(compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
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		    (const_int 0)))
   (set (match_operand:DI 0 "gpc_reg_operand" "")
	(zero_extend:DI (match_dup 1)))]
  "TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 0)
	(zero_extend:DI (match_dup 1)))
   (set (match_dup 2)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")
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(define_insn "*zero_extendsidi2_lfiwzx"
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  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
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	(zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
  "TARGET_POWERPC64 && TARGET_LFIWZX"
  "@
   lwz%U1%X1 %0,%1
   rldicl %0,%1,0,32
   mtvsrwz %x0,%1
   lfiwzx %0,%y1
   lxsiwzx %x0,%y1"
  [(set_attr_alternative "type"
      [(if_then_else
	 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
	 (const_string "load_ux")
	 (if_then_else
	   (match_test "update_address_mem (operands[1], VOIDmode)")
	   (const_string "load_u")
	   (const_string "load")))
       (const_string "*")
       (const_string "mffgpr")
       (const_string "fpload")
       (const_string "fpload")])])

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(define_insn "extendqidi2"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
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  "TARGET_POWERPC64"
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  "extsb %0,%1"
  [(set_attr "type" "exts")])
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(define_insn ""
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  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
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   (clobber (match_scratch:DI 2 "=r,r"))]
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  "TARGET_64BIT"
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  "@
   extsb. %2,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
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  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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	(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:DI 2 ""))]
  "TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 2)
	(sign_extend:DI (match_dup 1)))
   (set (match_dup 0)
	(compare:CC (match_dup 2)
		    (const_int 0)))]
  "")
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(define_insn ""
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  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
	(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
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   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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	(sign_extend:DI (match_dup 1)))]
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  "TARGET_64BIT"
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  "@
   extsb. %0,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
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  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
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	(compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (set (match_operand:DI 0 "gpc_reg_operand" "")
	(sign_extend:DI (match_dup 1)))]
  "TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 0)
	(sign_extend:DI (match_dup 1)))
   (set (match_dup 2)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")
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(define_expand "extendhidi2"
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
	(sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
  "TARGET_POWERPC64"
  "")

(define_insn ""
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
	(sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
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  "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
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  "@
   lha%U1%X1 %0,%1
   extsh %0,%1"
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  [(set_attr_alternative "type"
      [(if_then_else
	 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
	 (const_string "load_ext_ux")
	 (if_then_else
	   (match_test "update_address_mem (operands[1], VOIDmode)")
	   (const_string "load_ext_u")
	   (const_string "load_ext")))
       (const_string "exts")])])
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(define_insn ""
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
  "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
  "extsh %0,%1"
  [(set_attr "type" "exts")])

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(define_insn ""
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  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
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   (clobber (match_scratch:DI 2 "=r,r"))]
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  "TARGET_64BIT"
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  "@
   extsh. %2,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
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  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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	(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:DI 2 ""))]
  "TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 2)
	(sign_extend:DI (match_dup 1)))
   (set (match_dup 0)
	(compare:CC (match_dup 2)
		    (const_int 0)))]
  "")
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(define_insn ""
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  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
	(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
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   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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	(sign_extend:DI (match_dup 1)))]
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  "TARGET_64BIT"
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  "@
   extsh. %0,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
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  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
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	(compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (set (match_operand:DI 0 "gpc_reg_operand" "")
	(sign_extend:DI (match_dup 1)))]
  "TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 0)
	(sign_extend:DI (match_dup 1)))
   (set (match_dup 2)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")
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(define_expand "extendsidi2"
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
	(sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
  "TARGET_POWERPC64"
  "")

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(define_insn "*extendsidi2_lfiwax"
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  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
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	(sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
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  "TARGET_POWERPC64 && TARGET_LFIWAX"
  "@
   lwa%U1%X1 %0,%1
   extsw %0,%1
   mtvsrwa %x0,%1
   lfiwax %0,%y1
   lxsiwax %x0,%y1"
  [(set_attr_alternative "type"
      [(if_then_else
	 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
	 (const_string "load_ext_ux")
	 (if_then_else
	   (match_test "update_address_mem (operands[1], VOIDmode)")
	   (const_string "load_ext_u")
	   (const_string "load_ext")))
       (const_string "exts")
       (const_string "mffgpr")
       (const_string "fpload")
       (const_string "fpload")])])

(define_insn "*extendsidi2_nocell"
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  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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	(sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r")))]
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  "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX"
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  "@
   lwa%U1%X1 %0,%1
   extsw %0,%1"
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  [(set_attr_alternative "type"
      [(if_then_else
	 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
	 (const_string "load_ext_ux")
	 (if_then_else
	   (match_test "update_address_mem (operands[1], VOIDmode)")
	   (const_string "load_ext_u")
	   (const_string "load_ext")))
       (const_string "exts")])])
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(define_insn "*extendsidi2_nocell"
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  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
	(sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
  "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
  "extsw %0,%1"
  [(set_attr "type" "exts")])

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(define_insn ""
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  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
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   (clobber (match_scratch:DI 2 "=r,r"))]
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  "TARGET_64BIT"
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  "@
   extsw. %2,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
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  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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	(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:DI 2 ""))]
  "TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 2)
	(sign_extend:DI (match_dup 1)))
   (set (match_dup 0)
	(compare:CC (match_dup 2)
		    (const_int 0)))]
  "")
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(define_insn ""
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  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
	(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
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   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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	(sign_extend:DI (match_dup 1)))]
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  "TARGET_64BIT"
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  "@
   extsw. %0,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
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  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
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	(compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (set (match_operand:DI 0 "gpc_reg_operand" "")
	(sign_extend:DI (match_dup 1)))]
  "TARGET_POWERPC64 && reload_completed"
  [(set (match_dup 0)
	(sign_extend:DI (match_dup 1)))
   (set (match_dup 2)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")
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(define_expand "zero_extendqisi2"
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  [(set (match_operand:SI 0 "gpc_reg_operand" "")
	(zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
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  ""
  "")

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;; Catch the lbzux case for PPE42 as it does not support lbzux instruction
;; lbzux RT, RA,RB   RT is operand[0] RA,RB is operand[1]
;; replace with   add RA,RA,RB;; lbz RT, 0(RA)
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(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m")))]
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  "(rs6000_cpu == PROCESSOR_PPE42) &&
    update_indexed_address_mem (operands[1], VOIDmode)"
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  "*
{
    {
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    static char buf[40];
    int r1 = REGNO(XEXP(XEXP(operands[1],0),0));
    sprintf(buf,\"add %d,%%1 #lbzux\;lbz %%0,0(%d)\",r1,r1);
    return buf;
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    }
}"
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  [(set_attr "type" "load_ux")
   (set_attr "length" "8")])

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
  ""
  "@
   lbz%U1%X1 %0,%1
   rlwinm %0,%1,0,0xff"
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  [(set_attr_alternative "type"
      [(if_then_else
	 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
	 (const_string "load_ux")
	 (if_then_else
	   (match_test "update_address_mem (operands[1], VOIDmode)")
	   (const_string "load_u")
	   (const_string "load")))
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       (const_string "*")])])
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(define_insn ""
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  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
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   (clobber (match_scratch:SI 2 "=r,r"))]
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  ""
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  "@
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   andi. %2,%1,0xff
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   #"
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  [(set_attr "type" "fast_compare,compare")
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   (set_attr "length" "4,8")])

(define_split
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  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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	(compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:SI 2 ""))]
  "reload_completed"
  [(set (match_dup 2)
	(zero_extend:SI (match_dup 1)))
   (set (match_dup 0)
	(compare:CC (match_dup 2)
		    (const_int 0)))]
  "")
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941 942

(define_insn ""
943 944
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
	(compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
946
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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	(zero_extend:SI (match_dup 1)))]
  ""
949
  "@
950
   andi. %0,%1,0xff
951
   #"
952
  [(set_attr "type" "fast_compare,compare")
953 954 955
   (set_attr "length" "4,8")])

(define_split
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  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
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	(compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(zero_extend:SI (match_dup 1)))]
  "reload_completed"
  [(set (match_dup 0)
	(zero_extend:SI (match_dup 1)))
   (set (match_dup 2)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")
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969
(define_insn "extendqisi2"
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  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
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  ""
973 974
  "extsb %0,%1"
  [(set_attr "type" "exts")])
975 976

(define_insn ""
977 978
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
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   (clobber (match_scratch:SI 2 "=r,r"))]
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  ""
982 983 984 985 986 987 988
  "@
   extsb. %2,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
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  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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	(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:SI 2 ""))]
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  "reload_completed"
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  [(set (match_dup 2)
	(sign_extend:SI (match_dup 1)))
   (set (match_dup 0)
	(compare:CC (match_dup 2)
		    (const_int 0)))]
  "")
1000 1001

(define_insn ""
1002 1003
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
	(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
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   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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	(sign_extend:SI (match_dup 1)))]
1007
  ""
1008 1009 1010 1011 1012 1013 1014
  "@
   extsb. %0,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
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  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1016 1017 1018 1019
	(compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(sign_extend:SI (match_dup 1)))]
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  "reload_completed"
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  [(set (match_dup 0)
	(sign_extend:SI (match_dup 1)))
   (set (match_dup 2)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")
1027

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;; PPE42 does not support lbzux instruction
(define_insn ""
  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
	(zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m")))]
  "(rs6000_cpu == PROCESSOR_PPE42) &&
    update_indexed_address_mem (operands[1], VOIDmode)"
  "*
{
    {
        static char buf[40];
        int r1 = REGNO(XEXP(XEXP(operands[1],0),0));
        sprintf(buf,\"add %d,%%1 #lbzux\;lbz %%0,0(%d)\",r1,r1);
        return buf;
    }
}"
  [(set_attr "type" "load_ux")
   (set_attr "length" "8")])

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(define_insn ""
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  [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
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	(zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
  ""
  "@
1051
   lbz%U1%X1 %0,%1
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   rlwinm %0,%1,0,0xff"
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  [(set_attr_alternative "type"
      [(if_then_else
	 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
	 (const_string "load_ux")
	 (if_then_else
	   (match_test "update_address_mem (operands[1], VOIDmode)")
	   (const_string "load_u")
	   (const_string "load")))
       (const_string "*")])])
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(define_insn ""
1064 1065
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
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   (clobber (match_scratch:HI 2 "=r,r"))]
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  ""
1069
  "@
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   andi. %2,%1,0xff
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   #"
1072
  [(set_attr "type" "fast_compare,compare")
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   (set_attr "length" "4,8")])

(define_split
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  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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	(compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:HI 2 ""))]
  "reload_completed"
  [(set (match_dup 2)
	(zero_extend:HI (match_dup 1)))
   (set (match_dup 0)
	(compare:CC (match_dup 2)
		    (const_int 0)))]
  "")
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1088
(define_insn ""
1089 1090
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
	(compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
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   (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
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	(zero_extend:HI (match_dup 1)))]
  ""
1095
  "@
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   andi. %0,%1,0xff
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   #"
1098
  [(set_attr "type" "fast_compare,compare")
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   (set_attr "length" "4,8")])

(define_split
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  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
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	(compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (set (match_operand:HI 0 "gpc_reg_operand" "")
	(zero_extend:HI (match_dup 1)))]
  "reload_completed"
  [(set (match_dup 0)
	(zero_extend:HI (match_dup 1)))
   (set (match_dup 2)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")
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1115
(define_insn "extendqihi2"
1116 1117
  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
	(sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1118
  ""
1119 1120
  "extsb %0,%1"
  [(set_attr "type" "exts")])
1121 1122

(define_insn ""
1123 1124
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1125
		    (const_int 0)))
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   (clobber (match_scratch:HI 2 "=r,r"))]
1127
  ""
1128 1129 1130 1131 1132 1133 1134
  "@
   extsb. %2,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
1135
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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	(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:HI 2 ""))]
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  "reload_completed"
1140 1141 1142 1143 1144 1145
  [(set (match_dup 2)
	(sign_extend:HI (match_dup 1)))
   (set (match_dup 0)
	(compare:CC (match_dup 2)
		    (const_int 0)))]
  "")
1146 1147

(define_insn ""
1148 1149
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
	(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1150
		    (const_int 0)))
1151
   (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1152
	(sign_extend:HI (match_dup 1)))]
1153
  ""
1154 1155 1156 1157 1158 1159 1160
  "@
   extsb. %0,%1
   #"
  [(set_attr "type" "compare")
   (set_attr "length" "4,8")])

(define_split
1161
  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1162 1163 1164 1165
	(compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (set (match_operand:HI 0 "gpc_reg_operand" "")
	(sign_extend:HI (match_dup 1)))]
1166
  "reload_completed"
1167 1168 1169 1170 1171 1172
  [(set (match_dup 0)
	(sign_extend:HI (match_dup 1)))
   (set (match_dup 2)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")
1173

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1174
(define_expand "zero_extendhisi2"
1175
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
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1176
	(zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
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  ""
  "")

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;; PPE42 does not support lhzux instruction
(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m")))]
  "(rs6000_cpu == PROCESSOR_PPE42) &&
    update_indexed_address_mem (operands[1], VOIDmode)"
  "*
{
    {
        static char buf[40];
        int r1 = REGNO(XEXP(XEXP(operands[1],0),0));
        sprintf(buf,\"add %d,%%1 #lhzux\;lhz %%0,0(%d)\",r1,r1);
        return buf;
    }
}"
  [(set_attr "type" "load_ux")
   (set_attr "length" "8")])

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(define_insn ""
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  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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	(zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
  ""
  "@
   lhz%U1%X1 %0,%1
1204
   rlwinm %0,%1,0,0xffff"
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1205 1206 1207 1208 1209 1210 1211 1212 1213
  [(set_attr_alternative "type"
      [(if_then_else
	 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
	 (const_string "load_ux")
	 (if_then_else
	   (match_test "update_address_mem (operands[1], VOIDmode)")
	   (const_string "load_u")
	   (const_string "load")))
       (const_string "*")])])
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1214 1215

(define_insn ""
1216 1217
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
	(compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
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		    (const_int 0)))
1219
   (clobber (match_scratch:SI 2 "=r,r"))]
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  ""
1221
  "@
1222
   andi. %2,%1,0xffff
1223
   #"
1224
  [(set_attr "type" "fast_compare,compare")
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   (set_attr "length" "4,8")])

(define_split
1228
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1229 1230 1231 1232 1233 1234 1235 1236 1237 1238
	(compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (clobber (match_scratch:SI 2 ""))]
  "reload_completed"
  [(set (match_dup 2)
	(zero_extend:SI (match_dup 1)))
   (set (match_dup 0)
	(compare:CC (match_dup 2)
		    (const_int 0)))]
  "")
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1239 1240

(define_insn ""
1241 1242
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
	(compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
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1243
		    (const_int 0)))
1244
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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	(zero_extend:SI (match_dup 1)))]
  ""
1247
  "@
1248
   andi. %0,%1,0xffff
1249
   #"
1250
  [(set_attr "type" "fast_compare,compare")
1251 1252 1253
   (set_attr "length" "4,8")])

(define_split
1254
  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265
	(compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
		    (const_int 0)))
   (set (match_operand:SI 0 "gpc_reg_operand" "")
	(zero_extend:SI (match_dup 1)))]
  "reload_completed"
  [(set (match_dup 0)
	(zero_extend:SI (match_dup 1)))
   (set (match_dup 2)
	(compare:CC (match_dup 0)
		    (const_int 0)))]
  "")
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1266 1267

(define_expand "extendhisi2"
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  [(set (match_operand:SI 0 "gpc_reg_operand" "")
	(sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
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  ""
  "")

(define_insn ""
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  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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	(sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1276
  "rs6000_gen_cell_microcode"
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  "@
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1278
   lhz%U1%X1 %0,%1\;extsh %0,%0
1279
   extsh %0,%1"
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1280 1281 1282 1283 1284 1285 1286 1287
  [(set_attr_alternative "type"
      [(if_then_else
	 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
	 (const_string "load_ext_ux")
	 (if_then_else
	   (match_test "update_address_mem (operands[1], VOIDmode)")
	   (const_string "load_ext_u")
	   (const_string "load_ext")))
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       (const_string "exts")])
       (set_attr "length" "8,4")])
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