Commit a22429b9 authored by Nick Clifton's avatar Nick Clifton

* write.c (write_contents): Include output file name and bfd error

	value when reporting the inability to write to the output file.
	* config/tc-rx.c (rx_handle_align): Do not insert NOPs into align
	frag that has a non-zero fill value.

	* gas/all/align.d: Skip for the RX.
	* gas/elf/group1a.d: Likewise.
	* gas/elf/groupautoa.d: Likewise.
	* gas/elf/elf.exp: Do not run section5 test for the RX port.
	* gas/elf/section4.d: Likewise.
	* gas/elf/section7.d: Likewise.
	* gas/macros/semi.s: Fill with a non-zero pattern.
	* gas/macros/semi.d: Expect non-zero fill value.
	* gas/rx/bcnd.d: Update expected disassembly.
	* gas/rx/bra.d: Likewise.
	* gas/rx/macros.inc: Add reg1 macro.
	* gas/rx/max.sm: Use reg1 macro to avoid generating illegal NOP
	instruction.
	* gas/rx/mov.sm: Likewise.
	* gas/rx/max.d: Update expected disassembly.
	* gas/rx/mov.d: Likewise.
	* gas/rx/rx-asm-good.s: Use Renesas section names.
	* gas/rx/rx-asm-good.d: Update expected disassembly.
parent 45a43567
2011-01-31 Nick Clifton <nickc@redhat.com>
* write.c (write_contents): Include output file name and bfd error
value when reporting the inability to write to the output file.
* config/tc-rx.c (rx_handle_align): Do not insert NOPs into align
frag that has a non-zero fill value.
2011-01-27 DJ Delorie <dj@redhat.com>
* config/tc-rx.c (md_convert_frag): If we can't compute the target
......
......@@ -548,7 +548,7 @@ const pseudo_typeS md_pseudo_table[] =
/* The manual documents ".stk" but the compiler emits ".stack". */
{ "stack", rx_nop, 0 },
/* Theae are Renesas as100 assembler pseudo-ops that we do support. */
/* These are Renesas as100 assembler pseudo-ops that we do support. */
{ "addr", rx_cons, 3 },
{ "align", s_align_bytes, 2 },
{ "byte", rx_cons, 1 },
......@@ -1142,6 +1142,9 @@ static unsigned char *nops[] = { NULL, nop_1, nop_2, nop_3, nop_4, nop_5, nop_6,
void
rx_handle_align (fragS * frag)
{
/* If handling an alignment frag, use an optimal NOP pattern.
Only do this if a fill value has not already been provided.
FIXME: This test fails if the provided fill value is zero. */
if ((frag->fr_type == rs_align
|| frag->fr_type == rs_align_code)
&& subseg_text_p (now_seg))
......@@ -1151,16 +1154,19 @@ rx_handle_align (fragS * frag)
- frag->fr_fix);
unsigned char *base = (unsigned char *)frag->fr_literal + frag->fr_fix;
if (count > BIGGEST_NOP)
if (* base == 0)
{
base[0] = 0x2e;
base[1] = count;
frag->fr_var = 2;
}
else if (count > 0)
{
memcpy (base, nops[count], count);
frag->fr_var = count;
if (count > BIGGEST_NOP)
{
base[0] = 0x2e;
base[1] = count;
frag->fr_var = 2;
}
else if (count > 0)
{
memcpy (base, nops[count], count);
frag->fr_var = count;
}
}
}
......
2011-01-31 Nick Clifton <nickc@redhat.com>
* gas/all/align.d: Skip for the RX.
* gas/elf/group1a.d: Likewise.
* gas/elf/groupautoa.d: Likewise.
* gas/elf/elf.exp: Do not run section5 test for the RX port.
* gas/elf/section4.d: Likewise.
* gas/elf/section7.d: Likewise.
* gas/macros/semi.s: Fill with a non-zero pattern.
* gas/macros/semi.d: Expect non-zero fill value.
* gas/rx/bcnd.d: Update expected disassembly.
* gas/rx/bra.d: Likewise.
* gas/rx/macros.inc: Add reg1 macro.
* gas/rx/max.sm: Use reg1 macro to avoid generating illegal NOP
instruction.
* gas/rx/mov.sm: Likewise.
* gas/rx/max.d: Update expected disassembly.
* gas/rx/mov.d: Likewise.
* gas/rx/rx-asm-good.s: Use Renesas section names.
* gas/rx/rx-asm-good.d: Update expected disassembly.
2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
PR gas/12409
......
#objdump: -s -j .text
#name: align
#not-target: m32c-*
# The RX port will always replace zeros in any aligned area with NOPs,
# even if the user requested that they filled with zeros.
#not-target: m32c-* rx-*
# Test the alignment pseudo-op.
......
......@@ -146,9 +146,11 @@ if { ([istarget "*-*-*elf*"]
}
run_dump_test "section3"
run_dump_test "section4"
if {! [istarget "h8300-*-*"]} then {
if {! [istarget "h8300-*-*"] && ! [istarget "rx-*-*"]} then {
# The h8300 port issues a warning message for
# new sections created without atrributes.
# The RX port does not complain about changing the attributes of the
# .data and .bss sections since it does not use those names.
run_elf_list_test "section5" "" "-al" "-SW" "| grep \" \\\\.test\\\[0-9\\\]\""
}
run_dump_test "struct"
......
#readelf: -SW
#name: group section with multiple sections of same name
#source: group1.s
# The RX port uses non-standard section names.
#not-target: rx-*
#...
[ ]*\[.*\][ ]+\.group[ ]+GROUP.*
......
#readelf: -SW
#name: automatic section group a
#source: groupauto.s
# The RX port uses non-standard section names.
#not-target: rx-*
#...
[ ]*\[.*\][ ]+\.group[ ]+GROUP.*
......
#readelf: --sections
#name: label arithmetic with multiple same-name sections
# The RX port uses non-standard section names.
#not-target: rx-*
#...
[ ]*\[.*\][ ]+\.group[ ]+GROUP.*
......
#objdump: -s
#name: elf section7
# .pushsection always creates the named section, but the
# test harness translates ".text" into "P" for the RX...
#not-target: rx-*
.*: +file format .*
......
......@@ -5,5 +5,5 @@
.*: .*
Contents of section .text:
0000 3b203b20 3a203a20 00000000 00000000 ; ; : : ........
0010 00000000 00000000 00000000 00000000 ................
0000 3b203b20 3a203a20 11111111 11111111 ; ; : : ........
0010 11111111 11111111 11111111 11111111 ................
......@@ -11,4 +11,4 @@
colon
.ascii ": "
.p2align 5,0
.p2align 5,0x11
......@@ -96,9 +96,9 @@ Disassembly of section \.text:
82: R_RX_DIR16S_PCREL foo
84: 3a 00 80 beq\.w 0xffff8084
87: 3a ff 7f beq\.w 0x8086
8a: 3a fc 7f beq\.w 0x8086
8a: 3a 00 00 beq\.w 0x8a
8b: R_RX_DIR16S_PCREL foo
8d: 3b 00 80 bne\.w 0xffff808d
90: 3b ff 7f bne\.w 0x808f
93: 3b fc 7f bne\.w 0x808f
93: 3b 00 00 bne\.w 0x93
94: R_RX_DIR16S_PCREL foo
......@@ -24,7 +24,7 @@ Disassembly of section \.text:
1b: R_RX_DIR24S_PCREL foo
1e: 04 00 00 80 bra\.a 0xff80001e
22: 04 ff ff 7f bra\.a 0x800021
26: 04 fb ff 7f bra\.a 0x800021
26: 04 00 00 00 bra\.a 0x26
27: R_RX_DIR24S_PCREL foo
2a: 7f 40 bra\.l r0
2c: 7f 4f bra\.l r15
macro reg {r0;r15}
macro reg1 {r1;r15}
macro reg2 {r0;r14}
macro reg7 {r0;r7}
macro regPlo {r1;r7}
......
......@@ -22,8 +22,8 @@ Disassembly of section \.text:
45: fd 70 4f 00 00 00 80 max #0x80000000, r15
4c: fd 70 40 ff ff ff 7f max #0x7fffffff, r0
53: fd 70 4f ff ff ff 7f max #0x7fffffff, r15
5a: fc 13 00 max r0, r0
5d: fc 13 0f max r0, r15
5a: fc 13 10 max r1, r0
5d: fc 13 1f max r1, r15
60: fc 13 f0 max r15, r0
63: fc 13 ff max r15, r15
66: fc 10 00 max \[r0\]\.ub, r0
......
max #{imm},{reg}
max {reg},{reg}
max {reg1},{reg}
max {memx},{reg}
......@@ -102,16 +102,16 @@ Disassembly of section \.text:
f6: fb f2 00 00 00 80 mov\.l #0x80000000, r15
fc: fb 02 ff ff ff 7f mov\.l #0x7fffffff, r0
102: fb f2 ff ff ff 7f mov\.l #0x7fffffff, r15
108: cf 00 mov\.b r0, r0
10a: cf 0f mov\.b r0, r15
108: cf 10 mov\.b r1, r0
10a: cf 1f mov\.b r1, r15
10c: cf f0 mov\.b r15, r0
10e: cf ff mov\.b r15, r15
110: df 00 mov\.w r0, r0
112: df 0f mov\.w r0, r15
110: df 10 mov\.w r1, r0
112: df 1f mov\.w r1, r15
114: df f0 mov\.w r15, r0
116: df ff mov\.w r15, r15
118: ef 00 mov\.l r0, r0
11a: ef 0f mov\.l r0, r15
118: ef 10 mov\.l r1, r0
11a: ef 1f mov\.l r1, r15
11c: ef f0 mov\.l r15, r0
11e: ef ff mov\.l r15, r15
120: 3c 00 00 mov\.b #0, \[r0\]
......@@ -258,36 +258,36 @@ Disassembly of section \.text:
375: fe 6f 0f mov\.l \[r15, r0\], r15
378: fe 6f f0 mov\.l \[r15, r15\], r0
37b: fe 6f ff mov\.l \[r15, r15\], r15
37e: c3 00 mov\.b r0, \[r0\]
380: c3 f0 mov\.b r0, \[r15\]
382: c7 00 fc mov\.b r0, 252\[r0\]
385: c7 f0 fc mov\.b r0, 252\[r15\]
388: cb 00 fc ff mov\.b r0, 65532\[r0\]
38c: cb f0 fc ff mov\.b r0, 65532\[r15\]
37e: c3 01 mov\.b r1, \[r0\]
380: c3 f1 mov\.b r1, \[r15\]
382: c7 01 fc mov\.b r1, 252\[r0\]
385: c7 f1 fc mov\.b r1, 252\[r15\]
388: cb 01 fc ff mov\.b r1, 65532\[r0\]
38c: cb f1 fc ff mov\.b r1, 65532\[r15\]
390: c3 0f mov\.b r15, \[r0\]
392: c3 ff mov\.b r15, \[r15\]
394: c7 0f fc mov\.b r15, 252\[r0\]
397: c7 ff fc mov\.b r15, 252\[r15\]
39a: cb 0f fc ff mov\.b r15, 65532\[r0\]
39e: cb ff fc ff mov\.b r15, 65532\[r15\]
3a2: d3 00 mov\.w r0, \[r0\]
3a4: d3 f0 mov\.w r0, \[r15\]
3a6: d7 00 7e mov\.w r0, 252\[r0\]
3a9: d7 f0 7e mov\.w r0, 252\[r15\]
3ac: db 00 fe 7f mov\.w r0, 65532\[r0\]
3b0: db f0 fe 7f mov\.w r0, 65532\[r15\]
3a2: d3 01 mov\.w r1, \[r0\]
3a4: d3 f1 mov\.w r1, \[r15\]
3a6: d7 01 7e mov\.w r1, 252\[r0\]
3a9: d7 f1 7e mov\.w r1, 252\[r15\]
3ac: db 01 fe 7f mov\.w r1, 65532\[r0\]
3b0: db f1 fe 7f mov\.w r1, 65532\[r15\]
3b4: d3 0f mov\.w r15, \[r0\]
3b6: d3 ff mov\.w r15, \[r15\]
3b8: d7 0f 7e mov\.w r15, 252\[r0\]
3bb: d7 ff 7e mov\.w r15, 252\[r15\]
3be: db 0f fe 7f mov\.w r15, 65532\[r0\]
3c2: db ff fe 7f mov\.w r15, 65532\[r15\]
3c6: e3 00 mov\.l r0, \[r0\]
3c8: e3 f0 mov\.l r0, \[r15\]
3ca: e7 00 3f mov\.l r0, 252\[r0\]
3cd: e7 f0 3f mov\.l r0, 252\[r15\]
3d0: eb 00 ff 3f mov\.l r0, 65532\[r0\]
3d4: eb f0 ff 3f mov\.l r0, 65532\[r15\]
3c6: e3 01 mov\.l r1, \[r0\]
3c8: e3 f1 mov\.l r1, \[r15\]
3ca: e7 01 3f mov\.l r1, 252\[r0\]
3cd: e7 f1 3f mov\.l r1, 252\[r15\]
3d0: eb 01 ff 3f mov\.l r1, 65532\[r0\]
3d4: eb f1 ff 3f mov\.l r1, 65532\[r15\]
3d8: e3 0f mov\.l r15, \[r0\]
3da: e3 ff mov\.l r15, \[r15\]
3dc: e7 0f 3f mov\.l r15, 252\[r0\]
......
......@@ -6,7 +6,7 @@
mov.L #{uimm8},{reg}
mov.L #{imm},{reg}
mov{bwl} {reg},{reg}
mov{bwl} {reg1},{reg}
mov.B #{uimm8},{mem}
mov.W #{simm8},{mem}
......@@ -16,7 +16,7 @@
mov{bwl} {mem},{reg}
mov{bwl} [{reg},{reg}],{reg}
mov{bwl} {reg},{mem}
mov{bwl} {reg1},{mem}
mov{bwl} {reg},[{reg},{reg}]
mov{bwl} {mem},{mem}
......
# name: Compatibility with Renesas's own assembler
# objdump: -D --prefix-addresses --show-raw-insn
# section-subst: no
.*: +file format elf32-rx-.*
Disassembly of section .text:
Disassembly of section P:
.*
.*
0+0108 <mem\+0x8> 66 20[ ]+mov.l[ ]+#2, r0
......@@ -18,7 +17,7 @@ Disassembly of section .text:
0+011c <mem\+0x1c> ff 2e 00[ ]+add[ ]+r0, r0, r14
.*
Disassembly of section .data:
Disassembly of section D_1:
0+0000 <dmem> 01.*
0+0001 <dmem\+0x1> 00.*
0+0002 <dmem\+0x2> 00.*
......
.INCLUDE ..FILE@.inc
.SECTION .text,CODE,ALIGN
.SECTION P,CODE,ALIGN
.ORG 100H
......@@ -42,7 +42,7 @@ mem:
bra ?-
.SECTION .data,DATA
.SECTION D_1,DATA
.GLB dmem
dmem:
size .EQU 2
......
......@@ -1565,7 +1565,9 @@ write_contents (bfd *abfd ATTRIBUTE_UNUSED,
(stdoutput, sec, buf, (file_ptr) offset,
(bfd_size_type) n_per_buf * fill_size);
if (!x)
as_fatal (_("cannot write to output file"));
as_fatal (_("cannot write to output file '%s': %s"),
stdoutput->filename,
bfd_errmsg (bfd_get_error ()));
offset += n_per_buf * fill_size;
}
}
......
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