gas/

	* config/tc-aarch64.c (set_other_error): New function.
	(parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set
	the variable to which it points with 'o'.
	(parse_operands): Update; check for write to read-only system
	registers or read from write-only ones.

gas/testsuite/

	* gas/aarch64/diagnostic.s: Add tests.
	* gas/aarch64/diagnostic.l: Update.
	* gas/aarch64/tracereg-illegal.d: New file.
	* gas/aarch64/tracereg-illegal.l: Ditto.
	* gas/aarch64/tracereg-illegal.s: Ditto.
	* gas/aarch64/tracereg.d: Ditto.
	* gas/aarch64/tracereg.s: Ditto.

include/opcode

	* aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
	(aarch64_sys_reg_writeonly_p): Ditto.

opcodes/

	* aarch64-opc.c (CPENT): New define.
	(F_READONLY, F_WRITEONLY): Likewise.
	(aarch64_sys_regs): Add trace unit registers.
	(aarch64_sys_reg_readonly_p): New function.
	(aarch64_sys_reg_writeonly_p): Ditto.

gas/ChangeLog

+2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* config/tc-aarch64.c (set_other_error): New function.
+	(parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set
+	the variable to which it points with 'o'.
+	(parse_operands): Update; check for write to read-only system
+	registers or read from write-only ones.
+
 2013-11-15  H.J. Lu  <hongjiu.lu@intel.com>
 
 	Backport from master

gas/config/tc-aarch64.c

@@ -230,6 +230,12 @@ set_fatal_syntax_error (const char *error)
 {
   set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
 }
+
+static inline void
+set_other_error (const char *error)
+{
+  set_error (AARCH64_OPDE_OTHER_ERROR, error);
+}
 
 /* Number of littlenums required to hold an extended precision number.  */
 #define MAX_LITTLENUMS 6
@@ -3267,13 +3273,15 @@ parse_barrier (char **str)
 }
 
 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
-   Returns the encoding for the option, or PARSE_FAIL.
+   Returns the encoding for the option, or PARSE_FAIL.  If SYS_REG is not
+   NULL, return in *SYS_REG the found descriptor.
 
    If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
    implementation defined system register name S3_<op1>_<Cn>_<Cm>_<op2>.  */
 
 static int
-parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
+parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p,
+	       const aarch64_sys_reg ** sys_reg)
 {
   char *p, *q;
   char buf[32];
@@ -3320,6 +3328,9 @@ parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
       value = o->value;
     }
 
+  if (sys_reg)
+    *sys_reg = o;
+
   *str = q;
   return value;
 }
@@ -5180,17 +5191,31 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	  break;
 
 	case AARCH64_OPND_SYSREG:
-	  if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1))
-	      == PARSE_FAIL)
 	    {
-	      set_syntax_error (_("unknown or missing system register name"));
-	      goto failure;
+	      const aarch64_sys_reg *sys_reg = NULL;
+	      if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1,
+					&sys_reg))
+		  == PARSE_FAIL)
+		{
+		  set_syntax_error (_("unknown or missing system register name"));
+		  goto failure;
+		}
+	      else if (sys_reg && i == 0 && aarch64_sys_reg_readonly_p (sys_reg))
+		{
+		  set_other_error (_("read-only register"));
+		  goto failure;
+		}
+	      else if (sys_reg && i == 1 && aarch64_sys_reg_writeonly_p (sys_reg))
+		{
+		  set_other_error (_("write-only register"));
+		  goto failure;
+		}
+	      inst.base.operands[i].sysreg = val;
 	    }
-	  inst.base.operands[i].sysreg = val;
 	  break;
 
 	case AARCH64_OPND_PSTATEFIELD:
-	  if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0))
+	  if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, NULL))
 	      == PARSE_FAIL)
 	    {
 	      set_syntax_error (_("unknown or missing PSTATE field name"));

gas/testsuite/ChangeLog

+2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* gas/aarch64/diagnostic.s: Add tests.
+	* gas/aarch64/diagnostic.l: Update.
+	* gas/aarch64/tracereg-illegal.d: New file.
+	* gas/aarch64/tracereg-illegal.l: Ditto.
+	* gas/aarch64/tracereg-illegal.s: Ditto.
+	* gas/aarch64/tracereg.d: Ditto.
+	* gas/aarch64/tracereg.s: Ditto.
+
 2013-11-15  H.J. Lu  <hongjiu.lu@intel.com>
 
 	Backport from master

gas/testsuite/gas/aarch64/diagnostic.l

@@ -97,3 +97,5 @@
 [^:]*:99: Error: operand 3 should be one of the standard conditions, excluding AL and NV. -- `cinc w0,w1,nv'
 [^:]*:100: Error: operand 2 should be one of the standard conditions, excluding AL and NV. -- `cset w0,al'
 [^:]*:101: Error: operand 2 should be one of the standard conditions, excluding AL and NV. -- `cset w0,nv'
+[^:]*:102: Error: read-only register at operand 1 -- `msr trcidr7,x7'
+[^:]*:103: Error: write-only register at operand 2 -- `mrs x7,trcoslar'

gas/testsuite/gas/aarch64/diagnostic.s

@@ -99,3 +99,5 @@
 	cinc	w0, w1, nv
 	cset	w0, al
 	cset	w0, nv
+	msr	trcidr7, x7
+	mrs	x7, trcoslar

gas/testsuite/gas/aarch64/tracereg-illegal.d

+#name: Trace Unit Registers - Illegal Read/Write
+#as:
+#source: tracereg-illegal.s
+#error-output: tracereg-illegal.l

gas/testsuite/gas/aarch64/tracereg-illegal.l

+[^:]*: Assembler messages:
+[^:]*:35: Error: .*`msr trcstatr,x7'
+[^:]*:36: Error: .*`msr trcidr8,x7'
+[^:]*:37: Error: .*`msr trcidr9,x7'
+[^:]*:38: Error: .*`msr trcidr10,x7'
+[^:]*:39: Error: .*`msr trcidr11,x7'
+[^:]*:40: Error: .*`msr trcidr12,x7'
+[^:]*:41: Error: .*`msr trcidr13,x7'
+[^:]*:42: Error: .*`msr trcidr0,x7'
+[^:]*:43: Error: .*`msr trcidr1,x7'
+[^:]*:44: Error: .*`msr trcidr2,x7'
+[^:]*:45: Error: .*`msr trcidr3,x7'
+[^:]*:46: Error: .*`msr trcidr4,x7'
+[^:]*:47: Error: .*`msr trcidr5,x7'
+[^:]*:48: Error: .*`msr trcidr6,x7'
+[^:]*:49: Error: .*`msr trcidr7,x7'
+[^:]*:50: Error: .*`mrs x7,trcoslar'
+[^:]*:51: Error: .*`msr trcoslsr,x7'
+[^:]*:52: Error: .*`msr trcpdsr,x7'
+[^:]*:53: Error: .*`msr trcdevaff0,x7'
+[^:]*:54: Error: .*`msr trcdevaff1,x7'
+[^:]*:55: Error: .*`mrs x7,trclar'
+[^:]*:56: Error: .*`msr trclsr,x7'
+[^:]*:57: Error: .*`msr trcauthstatus,x7'
+[^:]*:58: Error: .*`msr trcdevarch,x7'
+[^:]*:59: Error: .*`msr trcdevid,x7'
+[^:]*:60: Error: .*`msr trcdevtype,x7'
+[^:]*:61: Error: .*`msr trcpidr4,x7'
+[^:]*:62: Error: .*`msr trcpidr5,x7'
+[^:]*:63: Error: .*`msr trcpidr6,x7'
+[^:]*:64: Error: .*`msr trcpidr7,x7'
+[^:]*:65: Error: .*`msr trcpidr0,x7'
+[^:]*:66: Error: .*`msr trcpidr1,x7'
+[^:]*:67: Error: .*`msr trcpidr2,x7'
+[^:]*:68: Error: .*`msr trcpidr3,x7'
+[^:]*:69: Error: .*`msr trccidr0,x7'
+[^:]*:70: Error: .*`msr trccidr1,x7'
+[^:]*:71: Error: .*`msr trccidr2,x7'
+[^:]*:72: Error: .*`msr trccidr3,x7'

gas/testsuite/gas/aarch64/tracereg-illegal.s

+/* tracereg-illegal.s Test file for AArch64 trace unit registers.
+   Reject writing to registers that are read-only and reading from
+   registers that are write-only.
+
+   Copyright 2013 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the license, or
+   (at your option) any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; see the file COPYING3. If not,
+   see <http://www.gnu.org/licenses/>.  */
+
+	.macro rw_sys_reg sys_reg xreg r w
+	.ifc \w, 1
+	msr \sys_reg, \xreg
+	.endif
+	.ifc \r, 1
+	mrs \xreg, \sys_reg
+	.endif
+	.endm
+
+	.text
+
+	rw_sys_reg sys_reg=trcstatr xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcidr8 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcidr9 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcidr10 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcidr11 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcidr12 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcidr13 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcidr0 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcidr1 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcidr2 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcidr3 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcidr4 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcidr5 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcidr6 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcidr7 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcoslar xreg=x7 r=1 w=0
+	rw_sys_reg sys_reg=trcoslsr xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcpdsr xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcdevaff0 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcdevaff1 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trclar xreg=x7 r=1 w=0
+	rw_sys_reg sys_reg=trclsr xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcauthstatus xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcdevarch xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcdevid xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcdevtype xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcpidr4 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcpidr5 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcpidr6 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcpidr7 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcpidr0 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcpidr1 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcpidr2 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trcpidr3 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trccidr0 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trccidr1 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trccidr2 xreg=x7 r=0 w=1
+	rw_sys_reg sys_reg=trccidr3 xreg=x7 r=0 w=1

include/opcode/ChangeLog

+2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
+	(aarch64_sys_reg_writeonly_p): Ditto.
+
 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 
 	* aarch64.h (aarch64_sys_reg): New typedef.

include/opcode/aarch64.h

@@ -624,6 +624,8 @@ typedef struct
 
 extern const aarch64_sys_reg aarch64_sys_regs [];
 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
+extern bfd_boolean aarch64_sys_reg_readonly_p (const aarch64_sys_reg *);
+extern bfd_boolean aarch64_sys_reg_writeonly_p (const aarch64_sys_reg *);
 
 typedef struct
 {

opcodes/ChangeLog

+2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-opc.c (CPENT): New define.
+	(F_READONLY, F_WRITEONLY): Likewise.
+	(aarch64_sys_regs): Add trace unit registers.
+	(aarch64_sys_reg_readonly_p): New function.
+	(aarch64_sys_reg_writeonly_p): Ditto.
+
 2013-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR gas/16140