Commit 34bca508 authored by H.J. Lu's avatar H.J. Lu

Remove trailing white spaces on gas

	* app.c: Remove trailing white spaces.
	* as.c: Likewise.
	* as.h: Likewise.
	* cond.c: Likewise.
	* dw2gencfi.c: Likewise.
	* dwarf2dbg.h: Likewise.
	* ecoff.c: Likewise.
	* input-file.c: Likewise.
	* itbl-lex.h: Likewise.
	* output-file.c: Likewise.
	* read.c: Likewise.
	* sb.c: Likewise.
	* subsegs.c: Likewise.
	* symbols.c: Likewise.
	* write.c: Likewise.
	* config/tc-i386.c: Likewise.
	* doc/Makefile.am: Likewise.
	* doc/Makefile.in: Likewise.
	* doc/c-aarch64.texi: Likewise.
	* doc/c-alpha.texi: Likewise.
	* doc/c-arc.texi: Likewise.
	* doc/c-arm.texi: Likewise.
	* doc/c-avr.texi: Likewise.
	* doc/c-bfin.texi: Likewise.
	* doc/c-cr16.texi: Likewise.
	* doc/c-d10v.texi: Likewise.
	* doc/c-d30v.texi: Likewise.
	* doc/c-h8300.texi: Likewise.
	* doc/c-hppa.texi: Likewise.
	* doc/c-i370.texi: Likewise.
	* doc/c-i386.texi: Likewise.
	* doc/c-i860.texi: Likewise.
	* doc/c-m32c.texi: Likewise.
	* doc/c-m32r.texi: Likewise.
	* doc/c-m68hc11.texi: Likewise.
	* doc/c-m68k.texi: Likewise.
	* doc/c-microblaze.texi: Likewise.
	* doc/c-mips.texi: Likewise.
	* doc/c-msp430.texi: Likewise.
	* doc/c-mt.texi: Likewise.
	* doc/c-s390.texi: Likewise.
	* doc/c-score.texi: Likewise.
	* doc/c-sh.texi: Likewise.
	* doc/c-sh64.texi: Likewise.
	* doc/c-tic54x.texi: Likewise.
	* doc/c-tic6x.texi: Likewise.
	* doc/c-v850.texi: Likewise.
	* doc/c-xc16x.texi: Likewise.
	* doc/c-xgate.texi: Likewise.
	* doc/c-xtensa.texi: Likewise.
	* doc/c-z80.texi: Likewise.
	* doc/internals.texi: Likewise.
parent 4c665b71
2013-01-10 H.J. Lu <hongjiu.lu@intel.com>
* app.c: Remove trailing white spaces.
* as.c: Likewise.
* as.h: Likewise.
* cond.c: Likewise.
* dw2gencfi.c: Likewise.
* dwarf2dbg.h: Likewise.
* ecoff.c: Likewise.
* input-file.c: Likewise.
* itbl-lex.h: Likewise.
* output-file.c: Likewise.
* read.c: Likewise.
* sb.c: Likewise.
* subsegs.c: Likewise.
* symbols.c: Likewise.
* write.c: Likewise.
* config/tc-i386.c: Likewise.
* doc/Makefile.am: Likewise.
* doc/Makefile.in: Likewise.
* doc/c-aarch64.texi: Likewise.
* doc/c-alpha.texi: Likewise.
* doc/c-arc.texi: Likewise.
* doc/c-arm.texi: Likewise.
* doc/c-avr.texi: Likewise.
* doc/c-bfin.texi: Likewise.
* doc/c-cr16.texi: Likewise.
* doc/c-d10v.texi: Likewise.
* doc/c-d30v.texi: Likewise.
* doc/c-h8300.texi: Likewise.
* doc/c-hppa.texi: Likewise.
* doc/c-i370.texi: Likewise.
* doc/c-i386.texi: Likewise.
* doc/c-i860.texi: Likewise.
* doc/c-m32c.texi: Likewise.
* doc/c-m32r.texi: Likewise.
* doc/c-m68hc11.texi: Likewise.
* doc/c-m68k.texi: Likewise.
* doc/c-microblaze.texi: Likewise.
* doc/c-mips.texi: Likewise.
* doc/c-msp430.texi: Likewise.
* doc/c-mt.texi: Likewise.
* doc/c-s390.texi: Likewise.
* doc/c-score.texi: Likewise.
* doc/c-sh.texi: Likewise.
* doc/c-sh64.texi: Likewise.
* doc/c-tic54x.texi: Likewise.
* doc/c-tic6x.texi: Likewise.
* doc/c-v850.texi: Likewise.
* doc/c-xc16x.texi: Likewise.
* doc/c-xgate.texi: Likewise.
* doc/c-xtensa.texi: Likewise.
* doc/c-z80.texi: Likewise.
* doc/internals.texi: Likewise.
2013-01-10 Roland McGrath <mcgrathr@google.com>
* hash.c (hash_new_sized): Make it global.
......
......@@ -684,7 +684,7 @@ do_scrub_chars (size_t (*get) (char *, size_t), char *tostart, size_t tolen)
case 16:
/* We have seen an 'a' at the start of a symbol, look for an 'f'. */
ch = GET ();
if (ch == 'f' || ch == 'F')
if (ch == 'f' || ch == 'F')
{
state = 17;
PUT (ch);
......@@ -1330,12 +1330,12 @@ do_scrub_chars (size_t (*get) (char *, size_t), char *tostart, size_t tolen)
#ifdef TC_Z80
/* "af'" is a symbol containing '\''. */
if (state == 3 && (ch == 'a' || ch == 'A'))
if (state == 3 && (ch == 'a' || ch == 'A'))
{
state = 16;
PUT (ch);
ch = GET ();
if (ch == 'f' || ch == 'F')
if (ch == 'f' || ch == 'F')
{
state = 17;
PUT (ch);
......
......@@ -25,9 +25,9 @@
Understands command arguments.
Has a few routines that don't fit in other modules because they
are shared.
bugs
: initialisers
Since no-one else says they will support them in future: I
don't support them now. */
......@@ -368,7 +368,7 @@ Options:\n\
--listing-cont-lines set the maximum number of continuation lines used\n\
for the output data column of the listing\n"));
fprintf (stream, _("\
@FILE read options from FILE\n"));
@FILE read options from FILE\n"));
md_show_usage (stream);
......@@ -460,7 +460,7 @@ parse_args (int * pargc, char *** pargv)
/* When you add options here, check that they do
not collide with OPTION_MD_BASE. See as.h. */
};
static const struct option std_longopts[] =
{
/* Note: commas are placed at the start of the line rather than
......@@ -1267,7 +1267,7 @@ main (int argc, char ** argv)
gnustack = subseg_new (".note.GNU-stack", 0);
bfd_set_section_flags (stdoutput, gnustack,
SEC_READONLY | (flag_execstack ? SEC_CODE : 0));
}
#endif
......@@ -1275,7 +1275,7 @@ main (int argc, char ** argv)
assembly debugging or on behalf of the compiler, emit it now. */
dwarf2_finish ();
/* If we constructed dwarf2 .eh_frame info, either via .cfi
/* If we constructed dwarf2 .eh_frame info, either via .cfi
directives from the user or by the backend, emit it now. */
cfi_finish ();
......
......@@ -23,13 +23,13 @@
#ifndef GAS
#define GAS 1
/* I think this stuff is largely out of date. xoxorich.
CAPITALISED names are #defined.
"lowercaseH" is #defined if "lowercase.h" has been #include-d.
"lowercaseT" is a typedef of "lowercase" objects.
"lowercaseP" is type "pointer to object of type 'lowercase'".
"lowercaseS" is typedef struct ... lowercaseS.
#define DEBUG to enable all the "know" assertion tests.
#define SUSPECT when debugging hash code.
#define COMMON as "extern" for all modules except one, where you #define
......
......@@ -91,7 +91,7 @@ s_ifdef (int test_defined)
*input_line_pointer = c;
initialize_cframe (&cframe);
if (cframe.dead_tree)
cframe.ignoring = 1;
else
......@@ -191,7 +191,7 @@ s_ifb (int test_blank)
struct conditional_frame cframe;
initialize_cframe (&cframe);
if (cframe.dead_tree)
cframe.ignoring = 1;
else
......
......@@ -6846,8 +6846,8 @@ lex_got (enum bfd_reloc_code_real *rel,
input string, minus the `@SECREL32' into a malloc'd buffer for
parsing by the calling routine. Return this buffer, and if ADJUST
is non-null set it to the length of the string we removed from the
input line. Otherwise return NULL.
input line. Otherwise return NULL.
This function is copied from the ELF version above adjusted for PE targets. */
static char *
......
......@@ -6,12 +6,12 @@
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
......@@ -32,7 +32,7 @@ POD2MAN = pod2man --center="GNU Development Tools" \
man_MANS = as.1
info_TEXINFOS = as.texinfo
info_TEXINFOS = as.texinfo
as_TEXINFOS = asconfig.texi $(CPU_DOCS)
AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
......
......@@ -22,12 +22,12 @@
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
......@@ -279,7 +279,7 @@ POD2MAN = pod2man --center="GNU Development Tools" \
--release="binutils-$(VERSION)" --section=1
man_MANS = as.1
info_TEXINFOS = as.texinfo
info_TEXINFOS = as.texinfo
as_TEXINFOS = asconfig.texi $(CPU_DOCS)
AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
-I "$(top_srcdir)/../bfd/doc" -I ../../bfd/doc
......@@ -410,17 +410,17 @@ as.info: as.texinfo $(as_TEXINFOS)
fi; \
rm -rf $$backupdir; exit $$rc
as.dvi: as.texinfo $(as_TEXINFOS)
as.dvi: as.texinfo $(as_TEXINFOS)
TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \
MAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir)' \
$(TEXI2DVI) -o $@ `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo
as.pdf: as.texinfo $(as_TEXINFOS)
as.pdf: as.texinfo $(as_TEXINFOS)
TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \
MAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir)' \
$(TEXI2PDF) -o $@ `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo
as.html: as.texinfo $(as_TEXINFOS)
as.html: as.texinfo $(as_TEXINFOS)
rm -rf $(@:.html=.htp)
if $(MAKEINFOHTML) $(AM_MAKEINFOHTMLFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) \
-o $(@:.html=.htp) `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo; \
......
......@@ -104,7 +104,7 @@ Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
instructions can be generated by prefixing the label with
@samp{#:pg_hi21:} and @samp{#:lo12:} respectively.
For example to use 33-bit (+/-4GB) pc-relative addressing to
For example to use 33-bit (+/-4GB) pc-relative addressing to
load the address of @var{foo} into x0:
@smallexample
......@@ -236,7 +236,7 @@ should only be done if it is really necessary.
@cindex opcodes for AArch64
@code{@value{AS}} implements all the standard AArch64 opcodes. It also
implements several pseudo opcodes, including several synthetic load
instructions.
instructions.
@table @code
......
......@@ -48,7 +48,7 @@ assemble an instruction which will not execute on the target processor,
the assembler may either expand the instruction as a macro or issue an
error message. This option is equivalent to the @code{.arch} directive.
The following processor names are recognized:
The following processor names are recognized:
@code{21064},
@code{21064a},
@code{21066},
......@@ -167,7 +167,7 @@ The 32 floating-point registers are referred to as @samp{$f@var{n}}.
@cindex relocations, Alpha
Some of these relocations are available for ECOFF, but mostly
only for ELF. They are modeled after the relocation format
only for ELF. They are modeled after the relocation format
introduced in Digital Unix 4.0, but there are additions.
The format is @samp{!@var{tag}} or @samp{!@var{tag}!@var{number}}
......@@ -243,13 +243,13 @@ jsr $26,($27),foo !lituse_jsr!1
@item !lituse_tlsgd!@var{N}
Used with a register branch format instruction to indicate that the
literal is the call to @code{__tls_get_addr} used to compute the
literal is the call to @code{__tls_get_addr} used to compute the
address of the thread-local storage variable whose descriptor was
loaded with @code{!tlsgd!@var{N}}.
@item !lituse_tlsldm!@var{N}
Used with a register branch format instruction to indicate that the
literal is the call to @code{__tls_get_addr} used to compute the
literal is the call to @code{__tls_get_addr} used to compute the
address of the base of the thread-local storage block for the current
module. The descriptor for the module must have been loaded with
@code{!tlsldm!@var{N}}.
......@@ -259,7 +259,7 @@ Used with @code{ldah} and @code{lda} to load the GP from the current
address, a-la the @code{ldgp} macro. The source register for the
@code{ldah} instruction must contain the address of the @code{ldah}
instruction. There must be exactly one @code{lda} instruction paired
with the @code{ldah} instruction, though it may appear anywhere in
with the @code{ldah} instruction, though it may appear anywhere in
the instruction stream. The immediate operands must be zero.
@example
......@@ -401,8 +401,8 @@ used in some non-standard way and so the linker cannot elide the load of
the procedure vector during relaxation.
@item .usepv @var{function}, @var{which}
Used to indicate the use of the @code{$27} register, similar to
@code{.prologue}, but without the other semantics of needing to
Used to indicate the use of the @code{$27} register, similar to
@code{.prologue}, but without the other semantics of needing to
be inside an open @code{.ent}/@code{.end} block.
The @var{which} argument should be either @code{no}, indicating that
......
......@@ -151,10 +151,10 @@ using this directive. The first parameter is the @var{name} of the
new auxiallry register. The second parameter is the @var{address} of
the register in the auxiliary register memory map for the variant of
the ARC. The third parameter specifies the @var{mode} in which the
register can be operated is and it can be one of:
register can be operated is and it can be one of:
@table @code
@item r (readonly)
@item r (readonly)
@item w (write only)
@item r|w (read or write)
@end table
......@@ -178,7 +178,7 @@ specify extra condition codes with any values. For example:
@smallexample
.extCondCode is_busy,0x14
add.is_busy r1,r2,r3
bis_busy _main
@end smallexample
......@@ -187,10 +187,10 @@ specify extra condition codes with any values. For example:
@item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut}
Specifies an extension core register @var{name} for the application.
This allows a register @var{name} with a valid @var{regnum} between 0
and 60, with the following as valid values for @var{mode}
and 60, with the following as valid values for @var{mode}
@table @samp
@item @emph{r} (readonly)
@item @emph{r} (readonly)
@item @emph{w} (write only)
@item @emph{r|w} (read or write)
@end table
......@@ -222,7 +222,7 @@ by the user. The parameters are:
@table @bullet
@item @var{name}
Name of the extension instruction
Name of the extension instruction
@item @var{opcode}
Opcode to be used. (Bits 27:31 in the encoding). Valid values
......@@ -234,7 +234,7 @@ correct value also depends on @var{syntaxclass}
@item @var{suffixclass}
Determines the kinds of suffixes to be allowed. Valid values are
@code{SUFFIX_NONE}, @code{SUFFIX_COND},
@code{SUFFIX_NONE}, @code{SUFFIX_COND},
@code{SUFFIX_FLAG} which indicates the absence or presence of
conditional suffixes and flag setting by the extension instruction.
It is also possible to specify that an instruction sets the flags and
......@@ -246,9 +246,9 @@ following values:
@table @code
@item @code{SYNTAX_2OP}:
2 Operand Instruction
2 Operand Instruction
@item @code{SYNTAX_3OP}:
3 Operand Instruction
3 Operand Instruction
@end table
In addition there could be modifiers for the syntax class as described
......@@ -262,7 +262,7 @@ Modifies syntax class SYNTAX_3OP, specifying that the first operand
of a three-operand instruction must be an immediate (i.e., the result
is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with
SYNTAX_3OP as given in the example below. This could usually be used
to set the flags using specific instructions and not retain results.
to set the flags using specific instructions and not retain results.
@item @code{OP1_IMM_IMPLIED}:
Modifies syntax class SYNTAX_20P, it specifies that there is an
......@@ -270,7 +270,7 @@ implied immediate destination operand which does not appear in the
syntax. For example, if the source code contains an instruction like:
@smallexample
inst r1,r2
inst r1,r2
@end smallexample
it really means that the first argument is an implied immediate (that
......@@ -278,7 +278,7 @@ is, the result is discarded). This is the same as though the source
code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it
with SYNTAX_20P.
@end itemize
@end itemize
@end table
For example, defining 64-bit multiplier with immediate operands:
......@@ -290,7 +290,7 @@ For example, defining 64-bit multiplier with immediate operands:
The above specifies an extension instruction called mp64 which has 3 operands,
sets the flags, can be used with a condition code, for which the
first operand is an immediate. (Equivalent to discarding the result
first operand is an immediate. (Equivalent to discarding the result
of the operation).
@smallexample
......
......@@ -38,7 +38,7 @@
This option specifies the target processor. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
recognized:
recognized:
@code{arm1},
@code{arm2},
@code{arm250},
......@@ -131,25 +131,25 @@ recognized:
@code{i80200} (Intel XScale processor)
@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
and
@code{xscale}.
@code{xscale}.
The special name @code{all} may be used to allow the
assembler to accept instructions valid for any ARM processor.
In addition to the basic instruction set, the assembler can be told to
accept various extension mnemonics that extend the processor using the
In addition to the basic instruction set, the assembler can be told to
accept various extension mnemonics that extend the processor using the
co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
is equivalent to specifying @code{-mcpu=ep9312}.
is equivalent to specifying @code{-mcpu=ep9312}.
Multiple extensions may be specified, separated by a @code{+}. The
Multiple extensions may be specified, separated by a @code{+}. The
extensions should be specified in ascending alphabetical order.
Some extensions may be restricted to particular architectures; this is
Some extensions may be restricted to particular architectures; this is
documented in the list of extensions below.
Extension mnemonics may also be removed from those the assembler accepts.
This is done be prepending @code{no} to the option that adds the extension.
Extensions that are removed should be listed after all extensions which have
been added, again in ascending alphabetical order. For example,
Extension mnemonics may also be removed from those the assembler accepts.
This is done be prepending @code{no} to the option that adds the extension.
Extensions that are removed should be listed after all extensions which have
been added, again in ascending alphabetical order. For example,
@code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
......@@ -164,7 +164,7 @@ The following extensions are currently supported:
@code{os} (Operating System for v6M architecture),
@code{sec} (Security Extensions for v6K and v7-A architectures),
@code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
@code{virt} (Virtualization Extensions for v7-A architecture, implies
@code{virt} (Virtualization Extensions for v7-A architecture, implies
@code{idiv}),
and
@code{xscale}.
......@@ -173,8 +173,8 @@ and
@item -march=@var{architecture}[+@var{extension}@dots{}]
This option specifies the target architecture. The assembler will issue
an error message if an attempt is made to assemble an instruction which
will not execute on the target architecture. The following architecture
names are recognized:
will not execute on the target architecture. The following architecture
names are recognized:
@code{armv1},
@code{armv2},
@code{armv2a},
......@@ -218,7 +218,7 @@ extension options as the @code{-mcpu} option.
This option specifies the floating point format to assemble for. The
assembler will issue an error message if an attempt is made to assemble
an instruction which will not execute on the target floating point unit.
an instruction which will not execute on the target floating point unit.
The following format options are recognized:
@code{softfpa},
@code{fpe},
......@@ -260,14 +260,14 @@ In addition to determining which instructions are assembled, this option
also affects the way in which the @code{.double} assembler directive behaves
when assembling little-endian code.
The default is dependent on the processor selected. For Architecture 5 or
later, the default is to assembler for VFP instructions; for earlier
The default is dependent on the processor selected. For Architecture 5 or
later, the default is to assembler for VFP instructions; for earlier
architectures the default is to assemble for FPA instructions.
@cindex @code{-mthumb} command line option, ARM
@item -mthumb
This option specifies that the assembler should start assembling Thumb
instructions; that is, it should behave as though the file starts with a
instructions; that is, it should behave as though the file starts with a
@code{.code 16} directive.
@cindex @code{-mthumb-interwork} command line option, ARM
......@@ -303,7 +303,7 @@ Calling Standard.
@cindex @code{-matpcs} command line option, ARM
@item -matpcs
This option specifies that the output generated by the assembler should
This option specifies that the output generated by the assembler should
be marked as supporting the Arm/Thumb Procedure Calling Standard. If
enabled this option will cause the assembler to create an empty
debugging section in the object file called .arm.atpcs. Debuggers can
......@@ -546,13 +546,13 @@ boundary). This is for compatibility with ARM's own assembler.
Select the target architecture. Valid values for @var{name} are the same as
for the @option{-march} commandline option.
Specifying @code{.arch} clears any previously selected architecture
Specifying @code{.arch} clears any previously selected architecture
extensions.
@cindex @code{.arch_extension} directive, ARM
@item .arch_extension @var{name}
Add or remove an architecture extension to the target architecture. Valid
values for @var{name} are the same as those accepted as architectural
Add or remove an architecture extension to the target architecture. Valid
values for @var{name} are the same as those accepted as architectural
extensions by the @option{-mcpu} commandline option.
@code{.arch_extension} may be used multiple times to add or remove extensions
......@@ -592,7 +592,7 @@ selects Thumb, with the value 32 selecting ARM.
Select the target processor. Valid values for @var{name} are the same as
for the @option{-mcpu} commandline option.
Specifying @code{.cpu} clears any previously selected architecture
Specifying @code{.cpu} clears any previously selected architecture
extensions.
@c DDDDDDDDDDDDDDDDDDDDDDDDDD
......@@ -658,7 +658,7 @@ The @var{value} is either a @code{number}, @code{"string"}, or
@code{number, "string"} depending on the tag.
Note - the following legacy values are also accepted by @var{tag}:
@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
@code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
@cindex @code{.even} directive, ARM
......@@ -950,7 +950,7 @@ used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
@cindex opcodes for ARM
@code{@value{AS}} implements all the standard ARM opcodes. It also
implements several pseudo opcodes, including several synthetic load
instructions.
instructions.
@table @code
......@@ -964,7 +964,7 @@ This pseudo op will always evaluate to a legal ARM instruction that does
nothing. Currently it will evaluate to MOV r0, r0.
@cindex @code{LDR reg,=<label>} pseudo op, ARM
@item LDR
@item LDR
@smallexample
ldr <register> , = <expression>
@end smallexample
......@@ -989,7 +989,7 @@ the ADR instruction, then an error will be generated. This instruction
will not make use of the literal pool.
@cindex @code{ADRL reg,<label>} pseudo op, ARM
@item ADRL
@item ADRL
@smallexample
adrl <register> <label>
@end smallexample
......@@ -1065,12 +1065,12 @@ that G++ generates for the following C++ input:
@verbatim
void callee (int *);
int
caller ()
int
caller ()
{
int i;
callee (&i);
return i;
return i;
}
@end verbatim
......@@ -1127,7 +1127,7 @@ The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
op appears immediately before the first instruction of the function
while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
op appears immediately after the last instruction of the function.
These pseudo ops specify the range of the function.
These pseudo ops specify the range of the function.
Only the order of the other pseudos ops (e.g., @code{.setfp} or
@code{.pad}) matters; their exact locations are irrelevant. In the
......
......@@ -96,13 +96,13 @@ memory space and greater than 64K data space (MCU types: none).
Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K program
memory space and less than 64K data space (MCU types: atxmega64a3, atxmega64d3).
Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program
Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program
memory space and greater than 64K data space (MCU types: atxmega64a1,
atxmega64a1u).
Instruction set avrxmega6 is for the XMEGA AVR core with up to 256K program
memory space and less than 64K data space (MCU types: atxmega128a3,
atxmega128d3, atxmega192a3, atxmega128b1, atxmega192d3, atxmega256a3,
atxmega128d3, atxmega192a3, atxmega128b1, atxmega192d3, atxmega256a3,
atxmega256a3b, atxmega256a3bu, atxmega192d3).
Instruction set avrxmega7 is for the XMEGA AVR core with up to 256K program
......@@ -294,37 +294,37 @@ The following table summarizes the AVR opcodes, and their arguments.
S @r{immediate value from 0 to 7 (S = s << 4)}
? @r{use this opcode entry if no parameters, else use next opcode entry}
1001010010001000 clc
1001010011011000 clh
1001010011111000 cli
1001010010101000 cln
1001010011001000 cls
1001010011101000 clt
1001010010111000 clv
1001010010011000 clz
1001010000001000 sec
1001010001011000 seh
1001010001111000 sei
1001010000101000 sen
1001010001001000 ses
1001010001101000 set
1001010000111000 sev
1001010000011000 sez
1001010010001000 clc
1001010011011000 clh
1001010011111000 cli
1001010010101000 cln
1001010011001000 cls
1001010011101000 clt
1001010010111000 clv
1001010010011000 clz
1001010000001000 sec
1001010001011000 seh
1001010001111000 sei
1001010000101000 sen
1001010001001000 ses
1001010001101000 set
1001010000111000 sev
1001010000011000 sez
100101001SSS1000 bclr S
100101000SSS1000 bset S
1001010100001001 icall
1001010000001001 ijmp
1001010000001001 ijmp
1001010111001000 lpm ?
1001000ddddd010+ lpm r,z
1001010111011000 elpm ?
1001000ddddd011+ elpm r,z
0000000000000000 nop
1001010100001000 ret
1001010100011000 reti
0000000000000000 nop
1001010100001000 ret
1001010100011000 reti
1001010110001000 sleep
1001010110011000 break
1001010110101000 wdr
1001010111101000 spm
1001010110101000 wdr
1001010111101000 spm
000111rdddddrrrr adc r,r
000011rdddddrrrr add r,r
001000rdddddrrrr and r,r
......@@ -408,6 +408,6 @@ The following table summarizes the AVR opcodes, and their arguments.
100!000dddddee-+ ld r,e
10o0oo1rrrrrbooo std b,r
100!001rrrrree-+ st e,r
1001010100011001 eicall
1001010000011001 eijmp
1001010100011001 eicall
1001010000011001 eijmp
@end smallexample
......@@ -37,7 +37,7 @@ is not used in assembler. It's here such that GCC can easily pass down its
@code{-mcpu=} option. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
recognized:
recognized:
@code{bf504},
@code{bf506},
@code{bf512},
......@@ -97,7 +97,7 @@ One instruction may extend across multiple lines or more than one
instruction may appear on the same line. White space (space, tab,
comments or newline) may appear anywhere between tokens. A token must
not have embedded spaces. Tokens include numbers, register names,
keywords, user identifiers, and also some multicharacter special
keywords, user identifiers, and also some multicharacter special
symbols like "+=", "/*" or "||".
Comments are introduced by the @samp{#} character and extend to the
......@@ -109,7 +109,7 @@ this case the line can also be a logical line number directive
@item Instruction Delimiting
A semicolon must terminate every instruction. Sometimes a complete
instruction will consist of more than one operation. There are two
instruction will consist of more than one operation. There are two
cases where this occurs. The first is when two general operations
are combined. Normally a comma separates the different parts, as in
......@@ -136,9 +136,9 @@ R3.L, r3.l and r3.L are all equivalent input to the assembler.
Register names are reserved and may not be used as program identifiers.
Some operations (such as "Move Register") require a register pair.
Some operations (such as "Move Register") require a register pair.
Register pairs are always data registers and are denoted using a colon,
eg., R3:2. The larger number must be written firsts. Note that the
eg., R3:2. The larger number must be written firsts. Note that the
hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
Some instructions (such as --SP (Push Multiple)) require a group of
......@@ -147,7 +147,7 @@ the range enclosed in parentheses and separated by a colon, eg., (R7:3).
Again, the larger number appears first.
Portions of a particular register may be individually specified. This
is written with a dot (".") following the register name and then a
is written with a dot (".") following the register name and then a
letter denoting the desired portion. For 32-bit registers, ".H"
denotes the most significant ("High") portion. ".L" denotes the
least-significant portion. The subdivisions of the 40-bit registers
......@@ -171,7 +171,7 @@ extend beyond bit 31.
@item Data Registers
The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that
normally contain data for manipulation. These are abbreviated as
normally contain data for manipulation. These are abbreviated as
D-register or Dreg. Data registers can be accessed as 32-bit registers
or as two independent 16-bit registers. The least significant 16 bits
of each register is called the "low" half and is designated with ".L"
......
......@@ -22,22 +22,22 @@
@section CR16 Operand Qualifiers
@cindex CR16 Operand Qualifiers
The National Semiconductor CR16 target of @code{@value{AS}} has a few machine dependent operand qualifiers.
The National Semiconductor CR16 target of @code{@value{AS}} has a few machine dependent operand qualifiers.
Operand expression type qualifier is an optional field in the instruction operand, to determines the type of the expression field of an operand. The @code{@@} is required. CR16 architecture uses one of the following expression qualifiers:
@table @code
@item s
@item s
- @code{Specifies expression operand type as small}
@item m
@item m
- @code{Specifies expression operand type as medium}
@item l
@item l
- @code{Specifies expression operand type as large}
@item c
@item c
- @code{Specifies the CR16 Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.}