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/* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
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   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
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   2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
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   Free Software Foundation, Inc.
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   Written by Ian Lance Taylor, Cygnus Support.

   This file is part of GAS, the GNU Assembler.

   GAS is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 3, or (at your option)
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   any later version.

   GAS is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to the Free
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   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
   02110-1301, USA.  */
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#include "as.h"
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#include "safe-ctype.h"
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#include "subsegs.h"
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#include "dw2gencfi.h"
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#include "opcode/ppc.h"

#ifdef OBJ_ELF
#include "elf/ppc.h"
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#include "elf/ppc64.h"
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#include "dwarf2dbg.h"
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#endif

#ifdef TE_PE
#include "coff/pe.h"
#endif

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#ifdef OBJ_XCOFF
#include "coff/xcoff.h"
#include "libxcoff.h"
#endif

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/* This is the assembler for the PowerPC or POWER (RS/6000) chips.  */

/* Tell the main code what the endianness is.  */
extern int target_big_endian;

/* Whether or not, we've set target_big_endian.  */
static int set_target_endian = 0;

/* Whether to use user friendly register names.  */
#ifndef TARGET_REG_NAMES_P
#ifdef TE_PE
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#define TARGET_REG_NAMES_P TRUE
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#else
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#define TARGET_REG_NAMES_P FALSE
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#endif
#endif

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/* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST,
   HIGHESTA.  */

/* #lo(value) denotes the least significant 16 bits of the indicated.  */
#define PPC_LO(v) ((v) & 0xffff)

/* #hi(value) denotes bits 16 through 31 of the indicated value.  */
#define PPC_HI(v) (((v) >> 16) & 0xffff)

/* #ha(value) denotes the high adjusted value: bits 16 through 31 of
  the indicated value, compensating for #lo() being treated as a
  signed number.  */
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#define PPC_HA(v) PPC_HI ((v) + 0x8000)
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/* #higher(value) denotes bits 32 through 47 of the indicated value.  */
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#define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff)
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/* #highera(value) denotes bits 32 through 47 of the indicated value,
   compensating for #lo() being treated as a signed number.  */
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#define PPC_HIGHERA(v) PPC_HIGHER ((v) + 0x8000)
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/* #highest(value) denotes bits 48 through 63 of the indicated value.  */
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#define PPC_HIGHEST(v) (((v) >> 24 >> 24) & 0xffff)
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/* #highesta(value) denotes bits 48 through 63 of the indicated value,
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   compensating for #lo being treated as a signed number.  */
#define PPC_HIGHESTA(v) PPC_HIGHEST ((v) + 0x8000)
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#define SEX16(val) (((val) ^ 0x8000) - 0x8000)

/* For the time being on ppc64, don't report overflow on @h and @ha
   applied to constants.  */
#define REPORT_OVERFLOW_HI 0
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static bfd_boolean reg_names_p = TARGET_REG_NAMES_P;
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static void ppc_macro (char *, const struct powerpc_macro *);
static void ppc_byte (int);
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#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
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static void ppc_tc (int);
static void ppc_machine (int);
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#endif
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#ifdef OBJ_XCOFF
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static void ppc_comm (int);
static void ppc_bb (int);
static void ppc_bc (int);
static void ppc_bf (int);
static void ppc_biei (int);
static void ppc_bs (int);
static void ppc_eb (int);
static void ppc_ec (int);
static void ppc_ef (int);
static void ppc_es (int);
static void ppc_csect (int);
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static void ppc_dwsect (int);
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static void ppc_change_csect (symbolS *, offsetT);
static void ppc_function (int);
static void ppc_extern (int);
static void ppc_lglobl (int);
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static void ppc_ref (int);
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static void ppc_section (int);
static void ppc_named_section (int);
static void ppc_stabx (int);
static void ppc_rename (int);
static void ppc_toc (int);
static void ppc_xcoff_cons (int);
static void ppc_vbyte (int);
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#endif

#ifdef OBJ_ELF
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static void ppc_elf_cons (int);
static void ppc_elf_rdata (int);
static void ppc_elf_lcomm (int);
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static void ppc_elf_localentry (int);
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static void ppc_elf_abiversion (int);
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#endif

#ifdef TE_PE
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static void ppc_previous (int);
static void ppc_pdata (int);
static void ppc_ydata (int);
static void ppc_reldata (int);
static void ppc_rdata (int);
static void ppc_ualong (int);
static void ppc_znop (int);
static void ppc_pe_comm (int);
static void ppc_pe_section (int);
static void ppc_pe_function (int);
static void ppc_pe_tocd (int);
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#endif

/* Generic assembler global variables which must be defined by all
   targets.  */

#ifdef OBJ_ELF
/* This string holds the chars that always start a comment.  If the
   pre-processor is disabled, these aren't very useful.  The macro
   tc_comment_chars points to this.  We use this, rather than the
   usual comment_chars, so that we can switch for Solaris conventions.  */
static const char ppc_solaris_comment_chars[] = "#!";
static const char ppc_eabi_comment_chars[] = "#";

#ifdef TARGET_SOLARIS_COMMENT
const char *ppc_comment_chars = ppc_solaris_comment_chars;
#else
const char *ppc_comment_chars = ppc_eabi_comment_chars;
#endif
#else
const char comment_chars[] = "#";
#endif

/* Characters which start a comment at the beginning of a line.  */
const char line_comment_chars[] = "#";

/* Characters which may be used to separate multiple commands on a
   single line.  */
const char line_separator_chars[] = ";";

/* Characters which are used to indicate an exponent in a floating
   point number.  */
const char EXP_CHARS[] = "eE";

/* Characters which mean that a number is a floating point constant,
   as in 0d1.0.  */
const char FLT_CHARS[] = "dD";
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/* Anything that can start an operand needs to be mentioned here,
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   to stop the input scrubber eating whitespace.  */
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const char ppc_symbol_chars[] = "%[";
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/* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */
int ppc_cie_data_alignment;
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/* The dwarf2 minimum instruction length.  */
int ppc_dwarf2_line_min_insn_length;

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/* More than this number of nops in an alignment op gets a branch
   instead.  */
unsigned long nop_limit = 4;

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/* The type of processor we are assembling for.  This is one or more
   of the PPC_OPCODE flags defined in opcode/ppc.h.  */
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ppc_cpu_t ppc_cpu = 0;
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ppc_cpu_t sticky = 0;
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/* Value for ELF e_flags EF_PPC64_ABI.  */
unsigned int ppc_abiversion = 0;

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/* Flags set on encountering toc relocs.  */
enum {
  has_large_toc_reloc = 1,
  has_small_toc_reloc = 2
} toc_reloc_types;
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/* The target specific pseudo-ops which we support.  */

const pseudo_typeS md_pseudo_table[] =
{
  /* Pseudo-ops which must be overridden.  */
  { "byte",	ppc_byte,	0 },

#ifdef OBJ_XCOFF
  /* Pseudo-ops specific to the RS/6000 XCOFF format.  Some of these
     legitimately belong in the obj-*.c file.  However, XCOFF is based
     on COFF, and is only implemented for the RS/6000.  We just use
     obj-coff.c, and add what we need here.  */
  { "comm",	ppc_comm,	0 },
  { "lcomm",	ppc_comm,	1 },
  { "bb",	ppc_bb,		0 },
  { "bc",	ppc_bc,		0 },
  { "bf",	ppc_bf,		0 },
  { "bi",	ppc_biei,	0 },
  { "bs",	ppc_bs,		0 },
  { "csect",	ppc_csect,	0 },
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  { "dwsect",	ppc_dwsect,	0 },
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  { "data",	ppc_section,	'd' },
  { "eb",	ppc_eb,		0 },
  { "ec",	ppc_ec,		0 },
  { "ef",	ppc_ef,		0 },
  { "ei",	ppc_biei,	1 },
  { "es",	ppc_es,		0 },
  { "extern",	ppc_extern,	0 },
  { "function",	ppc_function,	0 },
  { "lglobl",	ppc_lglobl,	0 },
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  { "ref",	ppc_ref,	0 },
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  { "rename",	ppc_rename,	0 },
  { "section",	ppc_named_section, 0 },
  { "stabx",	ppc_stabx,	0 },
  { "text",	ppc_section,	't' },
  { "toc",	ppc_toc,	0 },
  { "long",	ppc_xcoff_cons,	2 },
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  { "llong",	ppc_xcoff_cons,	3 },
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  { "word",	ppc_xcoff_cons,	1 },
  { "short",	ppc_xcoff_cons,	1 },
  { "vbyte",    ppc_vbyte,	0 },
#endif

#ifdef OBJ_ELF
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  { "llong",	ppc_elf_cons,	8 },
  { "quad",	ppc_elf_cons,	8 },
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  { "long",	ppc_elf_cons,	4 },
  { "word",	ppc_elf_cons,	2 },
  { "short",	ppc_elf_cons,	2 },
  { "rdata",	ppc_elf_rdata,	0 },
  { "rodata",	ppc_elf_rdata,	0 },
  { "lcomm",	ppc_elf_lcomm,	0 },
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  { "localentry", ppc_elf_localentry,	0 },
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  { "abiversion", ppc_elf_abiversion,	0 },
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#endif

#ifdef TE_PE
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  /* Pseudo-ops specific to the Windows NT PowerPC PE (coff) format.  */
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  { "previous", ppc_previous,   0 },
  { "pdata",    ppc_pdata,      0 },
  { "ydata",    ppc_ydata,      0 },
  { "reldata",  ppc_reldata,    0 },
  { "rdata",    ppc_rdata,      0 },
  { "ualong",   ppc_ualong,     0 },
  { "znop",     ppc_znop,       0 },
  { "comm",	ppc_pe_comm,	0 },
  { "lcomm",	ppc_pe_comm,	1 },
  { "section",  ppc_pe_section, 0 },
  { "function",	ppc_pe_function,0 },
  { "tocd",     ppc_pe_tocd,    0 },
#endif

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#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
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  { "tc",	ppc_tc,		0 },
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  { "machine",  ppc_machine,    0 },
#endif
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  { NULL,	NULL,		0 }
};


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/* Predefined register names if -mregnames (or default for Windows NT).
   In general, there are lots of them, in an attempt to be compatible
   with a number of other Windows NT assemblers.  */
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/* Structure to hold information about predefined registers.  */
struct pd_reg
  {
    char *name;
    int value;
  };

/* List of registers that are pre-defined:

   Each general register has predefined names of the form:
   1. r<reg_num> which has the value <reg_num>.
   2. r.<reg_num> which has the value <reg_num>.

   Each floating point register has predefined names of the form:
   1. f<reg_num> which has the value <reg_num>.
   2. f.<reg_num> which has the value <reg_num>.

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   Each vector unit register has predefined names of the form:
   1. v<reg_num> which has the value <reg_num>.
   2. v.<reg_num> which has the value <reg_num>.

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   Each condition register has predefined names of the form:
   1. cr<reg_num> which has the value <reg_num>.
   2. cr.<reg_num> which has the value <reg_num>.

   There are individual registers as well:
   sp or r.sp     has the value 1
   rtoc or r.toc  has the value 2
   fpscr          has the value 0
   xer            has the value 1
   lr             has the value 8
   ctr            has the value 9
   pmr            has the value 0
   dar            has the value 19
   dsisr          has the value 18
   dec            has the value 22
   sdr1           has the value 25
   srr0           has the value 26
   srr1           has the value 27

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   The table is sorted. Suitable for searching by a binary search.  */
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static const struct pd_reg pre_defined_registers[] =
{
  { "cr.0", 0 },    /* Condition Registers */
  { "cr.1", 1 },
  { "cr.2", 2 },
  { "cr.3", 3 },
  { "cr.4", 4 },
  { "cr.5", 5 },
  { "cr.6", 6 },
  { "cr.7", 7 },

  { "cr0", 0 },
  { "cr1", 1 },
  { "cr2", 2 },
  { "cr3", 3 },
  { "cr4", 4 },
  { "cr5", 5 },
  { "cr6", 6 },
  { "cr7", 7 },

  { "ctr", 9 },

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  { "d.0", 0 },    /* Double Word Regs for PPE */
  { "d.1", 1 }, 
  { "d.2", 2 },    
  { "d.28", 28 },
  { "d.29", 29 },
  { "d.3", 3 },
  { "d.30", 30 },
  { "d.31", 31 },
  { "d.4", 4 },
  { "d.5", 5 },
  { "d.6", 6 },
  { "d.7", 7 },
  { "d.8", 8 },
  { "d.9", 9 },

  { "d0", 0 },     /* More Double Word Regs for PPE */
  { "d1", 1 },  
  { "d2", 2 },    
  { "d28", 28 },
  { "d29", 29 },
  { "d3", 3 },
  { "d30", 30 },
  { "d31", 31 },
  { "d4", 4 },
  { "d5", 5 },
  { "d6", 6 },
  { "d7", 7 },
  { "d8", 8 },
  { "d9", 9 },

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  { "dar", 19 },    /* Data Access Register */
  { "dec", 22 },    /* Decrementer */
  { "dsisr", 18 },  /* Data Storage Interrupt Status Register */

  { "f.0", 0 },     /* Floating point registers */
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  { "f.1", 1 },
  { "f.10", 10 },
  { "f.11", 11 },
  { "f.12", 12 },
  { "f.13", 13 },
  { "f.14", 14 },
  { "f.15", 15 },
  { "f.16", 16 },
  { "f.17", 17 },
  { "f.18", 18 },
  { "f.19", 19 },
  { "f.2", 2 },
  { "f.20", 20 },
  { "f.21", 21 },
  { "f.22", 22 },
  { "f.23", 23 },
  { "f.24", 24 },
  { "f.25", 25 },
  { "f.26", 26 },
  { "f.27", 27 },
  { "f.28", 28 },
  { "f.29", 29 },
  { "f.3", 3 },
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  { "f.30", 30 },
  { "f.31", 31 },
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  { "f.32", 32 },    /* Extended floating point scalar registers (ISA 2.06).  */
  { "f.33", 33 },
  { "f.34", 34 },
  { "f.35", 35 },
  { "f.36", 36 },
  { "f.37", 37 },
  { "f.38", 38 },
  { "f.39", 39 },
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  { "f.4", 4 },
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  { "f.40", 40 },
  { "f.41", 41 },
  { "f.42", 42 },
  { "f.43", 43 },
  { "f.44", 44 },
  { "f.45", 45 },
  { "f.46", 46 },
  { "f.47", 47 },
  { "f.48", 48 },
  { "f.49", 49 },
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  { "f.5", 5 },
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  { "f.50", 50 },
  { "f.51", 51 },
  { "f.52", 52 },
  { "f.53", 53 },
  { "f.54", 54 },
  { "f.55", 55 },
  { "f.56", 56 },
  { "f.57", 57 },
  { "f.58", 58 },
  { "f.59", 59 },
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  { "f.6", 6 },
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  { "f.60", 60 },
  { "f.61", 61 },
  { "f.62", 62 },
  { "f.63", 63 },
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  { "f.7", 7 },
  { "f.8", 8 },
  { "f.9", 9 },

  { "f0", 0 },
  { "f1", 1 },
  { "f10", 10 },
  { "f11", 11 },
  { "f12", 12 },
  { "f13", 13 },
  { "f14", 14 },
  { "f15", 15 },
  { "f16", 16 },
  { "f17", 17 },
  { "f18", 18 },
  { "f19", 19 },
  { "f2", 2 },
  { "f20", 20 },
  { "f21", 21 },
  { "f22", 22 },
  { "f23", 23 },
  { "f24", 24 },
  { "f25", 25 },
  { "f26", 26 },
  { "f27", 27 },
  { "f28", 28 },
  { "f29", 29 },
  { "f3", 3 },
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  { "f30", 30 },
  { "f31", 31 },
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  { "f32", 32 },    /* Extended floating point scalar registers (ISA 2.06).  */
  { "f33", 33 },
  { "f34", 34 },
  { "f35", 35 },
  { "f36", 36 },
  { "f37", 37 },
  { "f38", 38 },
  { "f39", 39 },
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  { "f4", 4 },
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  { "f40", 40 },
  { "f41", 41 },
  { "f42", 42 },
  { "f43", 43 },
  { "f44", 44 },
  { "f45", 45 },
  { "f46", 46 },
  { "f47", 47 },
  { "f48", 48 },
  { "f49", 49 },
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  { "f5", 5 },
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  { "f50", 50 },
  { "f51", 51 },
  { "f52", 52 },
  { "f53", 53 },
  { "f54", 54 },
  { "f55", 55 },
  { "f56", 56 },
  { "f57", 57 },
  { "f58", 58 },
  { "f59", 59 },
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  { "f6", 6 },
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  { "f60", 60 },
  { "f61", 61 },
  { "f62", 62 },
  { "f63", 63 },
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  { "f7", 7 },
  { "f8", 8 },
  { "f9", 9 },
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  { "fpscr", 0 },

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  /* Quantization registers used with pair single instructions.  */
  { "gqr.0", 0 },
  { "gqr.1", 1 },
  { "gqr.2", 2 },
  { "gqr.3", 3 },
  { "gqr.4", 4 },
  { "gqr.5", 5 },
  { "gqr.6", 6 },
  { "gqr.7", 7 },
  { "gqr0", 0 },
  { "gqr1", 1 },
  { "gqr2", 2 },
  { "gqr3", 3 },
  { "gqr4", 4 },
  { "gqr5", 5 },
  { "gqr6", 6 },
  { "gqr7", 7 },

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  { "lr", 8 },     /* Link Register */

  { "pmr", 0 },

  { "r.0", 0 },    /* General Purpose Registers */
  { "r.1", 1 },
  { "r.10", 10 },
  { "r.11", 11 },
  { "r.12", 12 },
  { "r.13", 13 },
  { "r.14", 14 },
  { "r.15", 15 },
  { "r.16", 16 },
  { "r.17", 17 },
  { "r.18", 18 },
  { "r.19", 19 },
  { "r.2", 2 },
  { "r.20", 20 },
  { "r.21", 21 },
  { "r.22", 22 },
  { "r.23", 23 },
  { "r.24", 24 },
  { "r.25", 25 },
  { "r.26", 26 },
  { "r.27", 27 },
  { "r.28", 28 },
  { "r.29", 29 },
  { "r.3", 3 },
  { "r.30", 30 },
  { "r.31", 31 },
  { "r.4", 4 },
  { "r.5", 5 },
  { "r.6", 6 },
  { "r.7", 7 },
  { "r.8", 8 },
  { "r.9", 9 },

  { "r.sp", 1 },   /* Stack Pointer */

  { "r.toc", 2 },  /* Pointer to the table of contents */

  { "r0", 0 },     /* More general purpose registers */
  { "r1", 1 },
  { "r10", 10 },
  { "r11", 11 },
  { "r12", 12 },
  { "r13", 13 },
  { "r14", 14 },
  { "r15", 15 },
  { "r16", 16 },
  { "r17", 17 },
  { "r18", 18 },
  { "r19", 19 },
  { "r2", 2 },
  { "r20", 20 },
  { "r21", 21 },
  { "r22", 22 },
  { "r23", 23 },
  { "r24", 24 },
  { "r25", 25 },
  { "r26", 26 },
  { "r27", 27 },
  { "r28", 28 },
  { "r29", 29 },
  { "r3", 3 },
  { "r30", 30 },
  { "r31", 31 },
  { "r4", 4 },
  { "r5", 5 },
  { "r6", 6 },
  { "r7", 7 },
  { "r8", 8 },
  { "r9", 9 },

  { "rtoc", 2 },  /* Table of contents */

  { "sdr1", 25 }, /* Storage Description Register 1 */

  { "sp", 1 },

  { "srr0", 26 }, /* Machine Status Save/Restore Register 0 */
  { "srr1", 27 }, /* Machine Status Save/Restore Register 1 */
635

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  { "v.0", 0 },     /* Vector (Altivec/VMX) registers */
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  { "v.1", 1 },
  { "v.10", 10 },
  { "v.11", 11 },
  { "v.12", 12 },
  { "v.13", 13 },
  { "v.14", 14 },
  { "v.15", 15 },
  { "v.16", 16 },
  { "v.17", 17 },
  { "v.18", 18 },
  { "v.19", 19 },
  { "v.2", 2 },
  { "v.20", 20 },
  { "v.21", 21 },
  { "v.22", 22 },
  { "v.23", 23 },
  { "v.24", 24 },
  { "v.25", 25 },
  { "v.26", 26 },
  { "v.27", 27 },
  { "v.28", 28 },
  { "v.29", 29 },
  { "v.3", 3 },
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  { "v.30", 30 },
  { "v.31", 31 },
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  { "v.4", 4 },
  { "v.5", 5 },
  { "v.6", 6 },
  { "v.7", 7 },
  { "v.8", 8 },
  { "v.9", 9 },
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  { "v0", 0 },
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  { "v1", 1 },
  { "v10", 10 },
  { "v11", 11 },
  { "v12", 12 },
  { "v13", 13 },
  { "v14", 14 },
  { "v15", 15 },
  { "v16", 16 },
  { "v17", 17 },
  { "v18", 18 },
  { "v19", 19 },
  { "v2", 2 },
  { "v20", 20 },
  { "v21", 21 },
  { "v22", 22 },
  { "v23", 23 },
  { "v24", 24 },
  { "v25", 25 },
  { "v26", 26 },
  { "v27", 27 },
  { "v28", 28 },
  { "v29", 29 },
  { "v3", 3 },
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  { "v30", 30 },
  { "v31", 31 },
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  { "v4", 4 },
  { "v5", 5 },
  { "v6", 6 },
  { "v7", 7 },
  { "v8", 8 },
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  { "v9", 9 },
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  { "vs.0", 0 },     /* Vector Scalar (VSX) registers (ISA 2.06).  */
  { "vs.1", 1 },
  { "vs.10", 10 },
  { "vs.11", 11 },
  { "vs.12", 12 },
  { "vs.13", 13 },
  { "vs.14", 14 },
  { "vs.15", 15 },
  { "vs.16", 16 },
  { "vs.17", 17 },
  { "vs.18", 18 },
  { "vs.19", 19 },
  { "vs.2", 2 },
  { "vs.20", 20 },
  { "vs.21", 21 },
  { "vs.22", 22 },
  { "vs.23", 23 },
  { "vs.24", 24 },
  { "vs.25", 25 },
  { "vs.26", 26 },
  { "vs.27", 27 },
  { "vs.28", 28 },
  { "vs.29", 29 },
  { "vs.3", 3 },
  { "vs.30", 30 },
  { "vs.31", 31 },
  { "vs.32", 32 },
  { "vs.33", 33 },
  { "vs.34", 34 },
  { "vs.35", 35 },
  { "vs.36", 36 },
  { "vs.37", 37 },
  { "vs.38", 38 },
  { "vs.39", 39 },
  { "vs.4", 4 },
  { "vs.40", 40 },
  { "vs.41", 41 },
  { "vs.42", 42 },
  { "vs.43", 43 },
  { "vs.44", 44 },
  { "vs.45", 45 },
  { "vs.46", 46 },
  { "vs.47", 47 },
  { "vs.48", 48 },
  { "vs.49", 49 },
  { "vs.5", 5 },
  { "vs.50", 50 },
  { "vs.51", 51 },
  { "vs.52", 52 },
  { "vs.53", 53 },
  { "vs.54", 54 },
  { "vs.55", 55 },
  { "vs.56", 56 },
  { "vs.57", 57 },
  { "vs.58", 58 },
  { "vs.59", 59 },
  { "vs.6", 6 },
  { "vs.60", 60 },
  { "vs.61", 61 },
  { "vs.62", 62 },
  { "vs.63", 63 },
  { "vs.7", 7 },
  { "vs.8", 8 },
  { "vs.9", 9 },

  { "vs0", 0 },
  { "vs1", 1 },
  { "vs10", 10 },
  { "vs11", 11 },
  { "vs12", 12 },
  { "vs13", 13 },
  { "vs14", 14 },
  { "vs15", 15 },
  { "vs16", 16 },
  { "vs17", 17 },
  { "vs18", 18 },
  { "vs19", 19 },
  { "vs2", 2 },
  { "vs20", 20 },
  { "vs21", 21 },
  { "vs22", 22 },
  { "vs23", 23 },
  { "vs24", 24 },
  { "vs25", 25 },
  { "vs26", 26 },
  { "vs27", 27 },
  { "vs28", 28 },
  { "vs29", 29 },
  { "vs3", 3 },
  { "vs30", 30 },
  { "vs31", 31 },
  { "vs32", 32 },
  { "vs33", 33 },
  { "vs34", 34 },
  { "vs35", 35 },
  { "vs36", 36 },
  { "vs37", 37 },
  { "vs38", 38 },
  { "vs39", 39 },
  { "vs4", 4 },
  { "vs40", 40 },
  { "vs41", 41 },
  { "vs42", 42 },
  { "vs43", 43 },
  { "vs44", 44 },
  { "vs45", 45 },
  { "vs46", 46 },
  { "vs47", 47 },
  { "vs48", 48 },
  { "vs49", 49 },
  { "vs5", 5 },
  { "vs50", 50 },
  { "vs51", 51 },
  { "vs52", 52 },
  { "vs53", 53 },
  { "vs54", 54 },
  { "vs55", 55 },
  { "vs56", 56 },
  { "vs57", 57 },
  { "vs58", 58 },
  { "vs59", 59 },
  { "vs6", 6 },
  { "vs60", 60 },
  { "vs61", 61 },
  { "vs62", 62 },
  { "vs63", 63 },
  { "vs7", 7 },
  { "vs8", 8 },
  { "vs9", 9 },

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  { "xer", 1 },

};

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#define REG_NAME_CNT	(sizeof (pre_defined_registers) / sizeof (struct pd_reg))
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/* Given NAME, find the register number associated with that name, return
   the integer value associated with the given name or -1 on failure.  */

static int
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reg_name_search (const struct pd_reg *regs, int regcount, const char *name)
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{
  int middle, low, high;
  int cmp;

  low = 0;
  high = regcount - 1;

  do
    {
      middle = (low + high) / 2;
      cmp = strcasecmp (name, regs[middle].name);
      if (cmp < 0)
	high = middle - 1;
      else if (cmp > 0)
	low = middle + 1;
      else
	return regs[middle].value;
    }
  while (low <= high);

  return -1;
}

/*
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 * Summary of register_name.
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 *
 * in:	Input_line_pointer points to 1st char of operand.
 *
 * out:	A expressionS.
 *      The operand may have been a register: in this case, X_op == O_register,
 *      X_add_number is set to the register number, and truth is returned.
 *	Input_line_pointer->(next non-blank) char after operand, or is in its
 *      original state.
 */

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static bfd_boolean
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register_name (expressionS *expressionP)
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{
  int reg_number;
  char *name;
  char *start;
  char c;

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  /* Find the spelling of the operand.  */
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  start = name = input_line_pointer;
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  if (name[0] == '%' && ISALPHA (name[1]))
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    name = ++input_line_pointer;

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  else if (!reg_names_p || !ISALPHA (name[0]))
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    return FALSE;
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  c = get_symbol_end ();
  reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT, name);

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  /* Put back the delimiting char.  */
  *input_line_pointer = c;

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  /* Look to see if it's in the register table.  */
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  if (reg_number >= 0)
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    {
      expressionP->X_op = O_register;
      expressionP->X_add_number = reg_number;
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      /* Make the rest nice.  */
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      expressionP->X_add_symbol = NULL;
      expressionP->X_op_symbol = NULL;
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      return TRUE;
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    }
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  /* Reset the line as if we had not done anything.  */
  input_line_pointer = start;
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  return FALSE;
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}

/* This function is called for each symbol seen in an expression.  It
   handles the special parsing which PowerPC assemblers are supposed
   to use for condition codes.  */

/* Whether to do the special parsing.  */
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static bfd_boolean cr_operand;
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/* Names to recognize in a condition code.  This table is sorted.  */
static const struct pd_reg cr_names[] =
{
  { "cr0", 0 },
  { "cr1", 1 },
  { "cr2", 2 },
  { "cr3", 3 },
  { "cr4", 4 },
  { "cr5", 5 },
  { "cr6", 6 },
  { "cr7", 7 },
  { "eq", 2 },
  { "gt", 1 },
  { "lt", 0 },
  { "so", 3 },
  { "un", 3 }
};

/* Parsing function.  This returns non-zero if it recognized an
   expression.  */

int
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ppc_parse_name (const char *name, expressionS *exp)
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{
  int val;

  if (! cr_operand)
    return 0;

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  if (*name == '%')
    ++name;
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  val = reg_name_search (cr_names, sizeof cr_names / sizeof cr_names[0],
			 name);
  if (val < 0)
    return 0;

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  exp->X_op = O_constant;
  exp->X_add_number = val;
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  return 1;
}

/* Local variables.  */

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/* Whether to target xcoff64/elf64.  */
static unsigned int ppc_obj64 = BFD_DEFAULT_TARGET_SIZE == 64;
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/* Opcode hash table.  */
static struct hash_control *ppc_hash;

/* Macro hash table.  */
static struct hash_control *ppc_macro_hash;

#ifdef OBJ_ELF
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/* What type of shared library support to use.  */
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static enum { SHLIB_NONE, SHLIB_PIC, SHLIB_MRELOCATABLE } shlib = SHLIB_NONE;
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/* Flags to set in the elf header.  */
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static flagword ppc_flags = 0;

/* Whether this is Solaris or not.  */
#ifdef TARGET_SOLARIS_COMMENT
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#define SOLARIS_P TRUE
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#else
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#define SOLARIS_P FALSE
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#endif

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static bfd_boolean msolaris = SOLARIS_P;
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#endif

#ifdef OBJ_XCOFF

/* The RS/6000 assembler uses the .csect pseudo-op to generate code
   using a bunch of different sections.  These assembler sections,
   however, are all encompassed within the .text or .data sections of
   the final output file.  We handle this by using different
   subsegments within these main segments.  */

/* Next subsegment to allocate within the .text segment.  */
static subsegT ppc_text_subsegment = 2;

/* Linked list of csects in the text section.  */
static symbolS *ppc_text_csects;

/* Next subsegment to allocate within the .data segment.  */
static subsegT ppc_data_subsegment = 2;

/* Linked list of csects in the data section.  */
static symbolS *ppc_data_csects;

/* The current csect.  */
static symbolS *ppc_current_csect;

/* The RS/6000 assembler uses a TOC which holds addresses of functions
   and variables.  Symbols are put in the TOC with the .tc pseudo-op.
   A special relocation is used when accessing TOC entries.  We handle
   the TOC as a subsegment within the .data segment.  We set it up if
   we see a .toc pseudo-op, and save the csect symbol here.  */
static symbolS *ppc_toc_csect;

/* The first frag in the TOC subsegment.  */
static fragS *ppc_toc_frag;

/* The first frag in the first subsegment after the TOC in the .data
   segment.  NULL if there are no subsegments after the TOC.  */
static fragS *ppc_after_toc_frag;

/* The current static block.  */
static symbolS *ppc_current_block;

/* The COFF debugging section; set by md_begin.  This is not the
   .debug section, but is instead the secret BFD section which will
   cause BFD to set the section number of a symbol to N_DEBUG.  */
static asection *ppc_coff_debug_section;

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/* Structure to set the length field of the dwarf sections.  */
struct dw_subsection {
  /* Subsections are simply linked.  */
  struct dw_subsection *link;

  /* The subsection number.  */
  subsegT subseg;

  /* Expression to compute the length of the section.  */
  expressionS end_exp;
};

static struct dw_section {
  /* Corresponding section.  */
  segT sect;

  /* Simply linked list of subsections with a label.  */
  struct dw_subsection *list_subseg;

  /* The anonymous subsection.  */
  struct dw_subsection *anon_subseg;
} dw_sections[XCOFF_DWSECT_NBR_NAMES];
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#endif /* OBJ_XCOFF */

#ifdef TE_PE

/* Various sections that we need for PE coff support.  */
static segT ydata_section;
static segT pdata_section;
static segT reldata_section;
static segT rdata_section;
static segT tocdata_section;

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/* The current section and the previous section. See ppc_previous.  */
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static segT ppc_previous_section;
static segT ppc_current_section;

#endif /* TE_PE */

#ifdef OBJ_ELF
symbolS *GOT_symbol;		/* Pre-defined "_GLOBAL_OFFSET_TABLE" */
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#define PPC_APUINFO_ISEL	0x40
#define PPC_APUINFO_PMR		0x41
#define PPC_APUINFO_RFMCI	0x42
#define PPC_APUINFO_CACHELCK	0x43
#define PPC_APUINFO_SPE		0x100
#define PPC_APUINFO_EFS		0x101
#define PPC_APUINFO_BRLOCK	0x102
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#define PPC_APUINFO_VLE		0x104
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/*
 * We keep a list of APUinfo
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 */
unsigned long *ppc_apuinfo_list;
unsigned int ppc_apuinfo_num;
unsigned int ppc_apuinfo_num_alloc;
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#endif /* OBJ_ELF */

#ifdef OBJ_ELF
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const char *const md_shortopts = "b:l:usm:K:VQ:";
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#else
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const char *const md_shortopts = "um:";
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#endif
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#define OPTION_NOPS (OPTION_MD_BASE + 0)
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const struct option md_longopts[] = {
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  {"nops", required_argument, NULL, OPTION_NOPS},
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  {NULL, no_argument, NULL, 0}
};
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const size_t md_longopts_size = sizeof (md_longopts);
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int
1110
md_parse_option (int c, char *arg)
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{
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  ppc_cpu_t new_cpu;

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  switch (c)
    {
    case 'u':
      /* -u means that any undefined symbols should be treated as
	 external, which is the default for gas anyhow.  */
      break;

#ifdef OBJ_ELF
    case 'l':
      /* Solaris as takes -le (presumably for little endian).  For completeness
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	 sake, recognize -be also.  */
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      if (strcmp (arg, "e") == 0)
	{
	  target_big_endian = 0;
	  set_target_endian = 1;
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	  if (ppc_cpu & PPC_OPCODE_VLE)
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	    as_bad (_("the use of -mvle requires big endian."));
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	}
      else
	return 0;

      break;

    case 'b':
      if (strcmp (arg, "e") == 0)
	{
	  target_big_endian = 1;
	  set_target_endian = 1;
	}
      else
	return 0;

      break;

    case 'K':
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      /* Recognize -K PIC.  */
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      if (strcmp (arg, "PIC") == 0 || strcmp (arg, "pic") == 0)
	{
	  shlib = SHLIB_PIC;
	  ppc_flags |= EF_PPC_RELOCATABLE_LIB;
	}
      else
	return 0;

      break;
#endif

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      /* a64 and a32 determine whether to use XCOFF64 or XCOFF32.  */
    case 'a':
      if (strcmp (arg, "64") == 0)
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	{
#ifdef BFD64
	  ppc_obj64 = 1;
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	  if (ppc_cpu & PPC_OPCODE_VLE)
	    as_bad (_("the use of -mvle requires -a32."));
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#else
	  as_fatal (_("%s unsupported"), "-a64");
#endif
	}
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      else if (strcmp (arg, "32") == 0)
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	ppc_obj64 = 0;
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      else
	return 0;
      break;
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    case 'm':
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      new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, arg);
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      if (new_cpu != 0)
	{
	  ppc_cpu = new_cpu;
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	  if (strcmp (arg, "vle") == 0)
	    {
	      if (set_target_endian && target_big_endian == 0)
		as_bad (_("the use of -mvle requires big endian."));
	      if (ppc_obj64)
		as_bad (_("the use of -mvle requires -a32."));
	    }
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	}
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      else if (strcmp (arg, "regnames") == 0)
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	reg_names_p = TRUE;
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      else if (strcmp (arg, "no-regnames") == 0)
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	reg_names_p = FALSE;
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#ifdef OBJ_ELF
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      /* -mrelocatable/-mrelocatable-lib -- warn about initializations
	 that require relocation.  */
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      else if (strcmp (arg, "relocatable") == 0)
	{
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	  shlib = SHLIB_MRELOCATABLE;
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	  ppc_flags |= EF_PPC_RELOCATABLE;
	}

      else if (strcmp (arg, "relocatable-lib") == 0)
	{
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	  shlib = SHLIB_MRELOCATABLE;
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	  ppc_flags |= EF_PPC_RELOCATABLE_LIB;
	}

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      /* -memb, set embedded bit.  */
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      else if (strcmp (arg, "emb") == 0)
	ppc_flags |= EF_PPC_EMB;

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      /* -mlittle/-mbig set the endianness.  */
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      else if (strcmp (arg, "little") == 0
	       || strcmp (arg, "little-endian") == 0)
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	{
	  target_big_endian = 0;
	  set_target_endian = 1;
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	  if (ppc_cpu & PPC_OPCODE_VLE)
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	    as_bad (_("the use of -mvle requires big endian."));
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	}

      else if (strcmp (arg, "big") == 0 || strcmp (arg, "big-endian") == 0)
	{
	  target_big_endian = 1;
	  set_target_endian = 1;
	}

      else if (strcmp (arg, "solaris") == 0)
	{
1236
	  msolaris = TRUE;
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	  ppc_comment_chars = ppc_solaris_comment_chars;
	}

      else if (strcmp (arg, "no-solaris") == 0)
	{
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	  msolaris = FALSE;
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	  ppc_comment_chars = ppc_eabi_comment_chars;
	}
#endif
      else
	{
	  as_bad (_("invalid switch -m%s"), arg);
	  return 0;
	}
      break;

#ifdef OBJ_ELF
      /* -V: SVR4 argument to print version ID.  */
    case 'V':
      print_version_id ();
      break;

      /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
	 should be emitted or not.  FIXME: Not implemented.  */
    case 'Q':
      break;

      /* Solaris takes -s to specify that .stabs go in a .stabs section,
	 rather than .stabs.excl, which is ignored by the linker.
	 FIXME: Not implemented.  */
    case 's':
      if (arg)
	return 0;

      break;
#endif

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    case OPTION_NOPS:
      {
	char *end;
	nop_limit = strtoul (optarg, &end, 0);
	if (*end)
	  as_bad (_("--nops needs a numeric argument"));
      }
      break;
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    default:
      return 0;
    }

  return 1;
}

void
1291
md_show_usage (FILE *stream)
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{
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  fprintf (stream, _("\
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PowerPC options:\n\
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-a32                    generate ELF32/XCOFF32\n\
-a64                    generate ELF64/XCOFF64\n\
-u                      ignored\n\
-mpwrx, -mpwr2          generate code for POWER/2 (RIOS2)\n\
-mpwr                   generate code for POWER (RIOS1)\n\
-m601                   generate code for PowerPC 601\n\
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-mppc, -mppc32, -m603, -m604\n\
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                        generate code for PowerPC 603/604\n\
-m403                   generate code for PowerPC 403\n\
-m405                   generate code for PowerPC 405\n\
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-mppe42                 generate code for PowerPC ppe\n\
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-m440                   generate code for PowerPC 440\n\
-m464                   generate code for PowerPC 464\n\
-m476                   generate code for PowerPC 476\n\
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-m7400, -m7410, -m7450, -m7455\n\
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                        generate code for PowerPC 7400/7410/7450/7455\n\
-m750cl                 generate code for PowerPC 750cl\n"));
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  fprintf (stream, _("\
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-mppc64, -m620          generate code for PowerPC 620/625/630\n\
-mppc64bridge           generate code for PowerPC 64, including bridge insns\n\
-mbooke                 generate code for 32-bit PowerPC BookE\n\
-ma2                    generate code for A2 architecture\n\
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-mpower4, -mpwr4        generate code for Power4 architecture\n\
-mpower5, -mpwr5, -mpwr5x\n\
                        generate code for Power5 architecture\n\
-mpower6, -mpwr6        generate code for Power6 architecture\n\
-mpower7, -mpwr7        generate code for Power7 architecture\n\
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-mpower8, -mpwr8        generate code for Power8 architecture\n\
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-mcell                  generate code for Cell Broadband Engine architecture\n\
-mcom                   generate code Power/PowerPC common instructions\n\
-many                   generate code for any architecture (PWR/PWRX/PPC)\n"));
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  fprintf (stream, _("\
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-maltivec               generate code for AltiVec\n\
-mvsx                   generate code for Vector-Scalar (VSX) instructions\n\
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-mhtm                   generate code for Hardware Transactional Memory\n\
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-me300                  generate code for PowerPC e300 family\n\
-me500, -me500x2        generate code for Motorola e500 core complex\n\
-me500mc,               generate code for Freescale e500mc core complex\n\
-me500mc64,             generate code for Freescale e500mc64 core complex\n\
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-me5500,                generate code for Freescale e5500 core complex\n\
-me6500,                generate code for Freescale e6500 core complex\n\
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-mspe                   generate code for Motorola SPE instructions\n\
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-mvle                   generate code for Freescale VLE instructions\n\
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-mtitan                 generate code for AppliedMicro Titan core complex\n\
-mregnames              Allow symbolic names for registers\n\
-mno-regnames           Do not allow symbolic names for registers\n"));
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#ifdef OBJ_ELF
1342
  fprintf (stream, _("\
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-mrelocatable           support for GCC's -mrelocatble option\n\
-mrelocatable-lib       support for GCC's -mrelocatble-lib option\n\
-memb                   set PPC_EMB bit in ELF flags\n\
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-mlittle, -mlittle-endian, -le\n\
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                        generate code for a little endian machine\n\
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-mbig, -mbig-endian, -be\n\
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                        generate code for a big endian machine\n\
-msolaris               generate code for Solaris\n\
-mno-solaris            do not generate code for Solaris\n\
1352
-K PIC                  set EF_PPC_RELOCATABLE_LIB in ELF flags\n\
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-V                      print assembler version number\n\
-Qy, -Qn                ignored\n"));
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#endif
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  fprintf (stream, _("\
-nops=count             when aligning, more than COUNT nops uses a branch\n"));
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}

/* Set ppc_cpu if it is not already set.  */

static void
1363
ppc_set_cpu (void)
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{
  const char *default_os  = TARGET_OS;
  const char *default_cpu = TARGET_CPU;

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  if ((ppc_cpu & ~(ppc_cpu_t) PPC_OPCODE_ANY) == 0)
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    {
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      if (ppc_obj64)
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	ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_64;
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      else if (strncmp (default_os, "aix", 3) == 0
	       && default_os[3] >= '4' && default_os[3] <= '9')
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	ppc_cpu |= PPC_OPCODE_COMMON;
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      else if (strncmp (default_os, "aix3", 4) == 0)
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	ppc_cpu |= PPC_OPCODE_POWER;
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      else if (strcmp (default_cpu, "rs6000") == 0)
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	ppc_cpu |= PPC_OPCODE_POWER;
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      else if (strncmp (default_cpu, "powerpc", 7) == 0)
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	ppc_cpu |= PPC_OPCODE_PPC;
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      else
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	as_fatal (_("unknown default cpu = %s, os = %s"),
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		  default_cpu, default_os);
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    }
}

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/* Figure out the BFD architecture to use.  This function and ppc_mach
   are called well before md_begin, when the output file is opened.  */
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enum bfd_architecture
1391
ppc_arch (void)
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{
  const char *default_cpu = TARGET_CPU;
  ppc_set_cpu ();

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  if ((ppc_cpu & (PPC_OPCODE_PPC | PPC_OPCODE_PPE)) != 0)
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    return bfd_arch_powerpc;
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  if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
    return bfd_arch_powerpc;
  if ((ppc_cpu & PPC_OPCODE_POWER) != 0)
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    return bfd_arch_rs6000;
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  if ((ppc_cpu & (PPC_OPCODE_COMMON | PPC_OPCODE_ANY)) != 0)
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    {
      if (strcmp (default_cpu, "rs6000") == 0)
	return bfd_arch_rs6000;
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      else if (strncmp (default_cpu, "powerpc", 7) == 0)
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	return bfd_arch_powerpc;
    }

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  as_fatal (_("neither Power nor PowerPC opcodes were selected."));
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  return bfd_arch_unknown;
}

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unsigned long
1415
ppc_mach (void)
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{
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  if (ppc_obj64)
    return bfd_mach_ppc64;
  else if (ppc_arch () == bfd_arch_rs6000)
    return bfd_mach_rs6k;
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  else if (ppc_cpu & PPC_OPCODE_TITAN)
    return bfd_mach_ppc_titan;
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  else if (ppc_cpu & PPC_OPCODE_VLE)
    return bfd_mach_ppc_vle;
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  else
    return bfd_mach_ppc;
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}

1429
extern char*
1430
ppc_target_format (void)
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{
#ifdef OBJ_COFF
#ifdef TE_PE
1434
  return target_big_endian ? "pe-powerpc" : "pe-powerpcle";
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#elif TE_POWERMAC
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  return "xcoff-powermac";
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#else
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#  ifdef TE_AIX5
1439
  return (ppc_obj64 ? "aix5coff64-rs6000" : "aixcoff-rs6000");
1440
#  else
1441
  return (ppc_obj64 ? "aixcoff64-rs6000" : "aixcoff-rs6000");
1442
#  endif
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#endif
#endif
#ifdef OBJ_ELF
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# ifdef TE_FreeBSD
  return (ppc_obj64 ? "elf64-powerpc-freebsd" : "elf32-powerpc-freebsd");
# elif defined (TE_VXWORKS)
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  return "elf32-powerpc-vxworks";
# else
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  return (target_big_endian
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	  ? (ppc_obj64 ? "elf64-powerpc" : "elf32-powerpc")
	  : (ppc_obj64 ? "elf64-powerpcle" : "elf32-powerpcle"));
1454
# endif
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#endif
}

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/* Validate one entry in powerpc_opcodes[] or vle_opcodes[].
   Return TRUE if there's a problem, otherwise FALSE.  */

static bfd_boolean
insn_validate (const struct powerpc_opcode *op)
{
  const unsigned char *o;
  unsigned long omask = op->mask;

  /* The mask had better not trim off opcode bits.  */
  if ((op->opcode & omask) != op->opcode)
    {
      as_bad (_("mask trims opcode bits for %s"), op->name);
      return TRUE;
    }

  /* The operands must not overlap the opcode or each other.  */
  for (o = op->operands; *o; ++o)
    {
      if (*o >= num_powerpc_operands)
        {
	  as_bad (_("operand index error for %s"), op->name);
	  return TRUE;
        }
      else
        {
	  const struct powerpc_operand *operand = &powerpc_operands[*o];
1485
	  if (operand->shift != (int) PPC_OPSHIFT_INV)
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	    {
	      unsigned long mask;

	      if (operand->shift >= 0)
		mask = operand->bitm << operand->shift;
	      else
		mask = operand->bitm >> -operand->shift;
	      if (omask & mask)
		{
		  as_bad (_("operand %d overlap in %s"),
			  (int) (o - op->operands), op->name);
		  return TRUE;
		}
	      omask |= mask;
	    }
        }
    }
  return FALSE;
}

1506
/* Insert opcodes and macros into hash tables.  Called at startup and
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   for .machine pseudo.  */
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1509 1510
static void
ppc_setup_opcodes (void)
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{
1512
  const struct powerpc_opcode *op;
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  const struct powerpc_opcode *op_end;
  const struct powerpc_macro *macro;
  const struct powerpc_macro *macro_end;
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  bfd_boolean bad_insn = FALSE;
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  if (ppc_hash != NULL)
    hash_die (ppc_hash);
  if (ppc_macro_hash != NULL)
    hash_die (ppc_macro_hash);
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  /* Insert the opcodes into a hash table.  */
  ppc_hash = hash_new ();

1526
  if (ENABLE_CHECKING)
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    {
1528
      unsigned int i;
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      /* An index into powerpc_operands is stored in struct fix
	 fx_pcrel_adjust which is 8 bits wide.  */
      gas_assert (num_powerpc_operands < 256);

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      /* Check operand masks.  Code here and in the disassembler assumes
	 all the 1's in the mask are contiguous.  */
      for (i = 0; i < num_powerpc_operands; ++i)
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	{
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	  unsigned long mask = powerpc_operands[i].bitm;
	  unsigned long right_bit;
	  unsigned int j;

	  right_bit = mask & -mask;
	  mask += right_bit;
	  right_bit = mask & -mask;
	  if (mask != right_bit)
	    {
	      as_bad (_("powerpc_operands[%d].bitm invalid"), i);
	      bad_insn = TRUE;
	    }
	  for (j = i + 1; j < num_powerpc_operands; ++j)
	    if (memcmp (&powerpc_operands[i], &powerpc_operands[j],
			sizeof (powerpc_operands[0])) == 0)
	      {
		as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"),
			j, i);
		bad_insn = TRUE;
	      }
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	}
    }

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  op_end = powerpc_opcodes + powerpc_num_opcodes;
  for (op = powerpc_opcodes; op < op_end; op++)
    {
1564
      if (ENABLE_CHECKING)
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	{
1566
	  if (op != powerpc_opcodes)
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	    {
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	      int old_opcode = PPC_OP (op[-1].opcode);
	      int new_opcode = PPC_OP (op[0].opcode);

#ifdef PRINT_OPCODE_TABLE
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	      printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%x\tmask: 0x%x\tflags: 0x%llx\n",
		      op->name, (unsigned int) (op - powerpc_opcodes),
		      (unsigned int) new_opcode, (unsigned int) op->opcode,
		      (unsigned int) op->mask, (unsigned long long) op->flags);
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#endif

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	      /* The major opcodes had better be sorted.  Code in the
		 disassembler assumes the insns are sorted according to
		 major opcode.  */
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	      if (new_opcode < old_opcode)
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		{
		  as_bad (_("major opcode is not sorted for %s"),
			  op->name);
		  bad_insn = TRUE;
		}
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	    }
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	  bad_insn |= insn_validate (op);
	}
1590

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      if ((ppc_cpu & op->flags) != 0
	  && !(ppc_cpu & op->deprecated))
	{
	  const char *retval;

	  retval = hash_insert (ppc_hash, op->name, (void *) op);
	  if (retval != NULL)
1598
	    {
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	      as_bad (_("duplicate instruction %s"),
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		      op->name);
	      bad_insn = TRUE;
	    }
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	}
    }
1605

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  if ((ppc_cpu & PPC_OPCODE_ANY) != 0)
    for (op = powerpc_opcodes; op < op_end; op++)
      hash_insert (ppc_hash, op->name, (void *) op);

  op_end = vle_opcodes + vle_num_opcodes;
  for (op = vle_opcodes; op < op_end; op++)
    {
      if (ENABLE_CHECKING)
	{
	  if (op != vle_opcodes)
	    {
	      unsigned old_seg, new_seg;

	      old_seg = VLE_OP (op[-1].opcode, op[-1].mask);
	      old_seg = VLE_OP_TO_SEG (old_seg);
	      new_seg = VLE_OP (op[0].opcode, op[0].mask);
	      new_seg = VLE_OP_TO_SEG (new_seg);

#ifdef PRINT_OPCODE_TABLE