From 614e283a6e2e6fce3efba230f5be8017a8929403 Mon Sep 17 00:00:00 2001
From: uweigand <uweigand@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Tue, 26 Aug 2003 14:53:53 +0000
Subject: [PATCH] * config/s390/s390.md ("*llgt_sisi",
"*llgt_sisi_split", "*llgt_didi", "*llgt_didi_split", "*llgt_sidi",
"*llgt_sidi_split"): New insns.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@70812 138bc75d-0d04-0410-961f-82ee72b054a4
---
gcc/ChangeLog | 5 +++
gcc/config/s390/s390.md | 71 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 76 insertions(+)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 481a92659b6..8fb59454caa 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2003-08-26 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * config/s390/s390.md ("*llgt_sisi", "*llgt_sisi_split", "*llgt_didi",
+ "*llgt_didi_split", "*llgt_sidi", "*llgt_sidi_split"): New insns.
+
2003-08-26 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.md ("*fmadddf", "*fmsubdf",
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index d9e65439af0..fa7203df47a 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -2439,6 +2439,77 @@
"llgh\t%0,%1"
[(set_attr "op_type" "RXY")])
+;
+; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
+;
+
+(define_insn "*llgt_sisi"
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
+ (const_int 2147483647)))]
+ "TARGET_64BIT"
+ "@
+ llgtr\t%0,%1
+ llgt\t%0,%1"
+ [(set_attr "op_type" "RRE,RXE")])
+
+(define_insn_and_split "*llgt_sisi_split"
+ [(set (match_operand:SI 0 "register_operand" "=d,d")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
+ (const_int 2147483647)))
+ (clobber (reg:CC 33))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (and:SI (match_dup 1)
+ (const_int 2147483647)))]
+ "")
+
+(define_insn "*llgt_didi"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
+ (const_int 2147483647)))]
+ "TARGET_64BIT"
+ "@
+ llgtr\t%0,%1
+ llgt\t%0,%N1"
+ [(set_attr "op_type" "RRE,RXE")])
+
+(define_insn_and_split "*llgt_didi_split"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
+ (const_int 2147483647)))
+ (clobber (reg:CC 33))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (and:DI (match_dup 1)
+ (const_int 2147483647)))]
+ "")
+
+(define_insn "*llgt_sidi"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
+ (const_int 2147483647)))]
+ "TARGET_64BIT"
+ "llgt\t%0,%1"
+ [(set_attr "op_type" "RXE")])
+
+(define_insn_and_split "*llgt_sidi_split"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
+ (const_int 2147483647)))
+ (clobber (reg:CC 33))]
+ "TARGET_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (and:DI (subreg:DI (match_dup 1) 0)
+ (const_int 2147483647)))]
+ "")
+
;
; zero_extendqidi2 instruction pattern(s)
;
--
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