From c0efd52b8b1951c20878208fdcbab0468f816804 Mon Sep 17 00:00:00 2001
From: Olof Johansson <olof@lixom.net>
Date: Wed, 22 Aug 2007 09:12:52 -0500
Subject: [PATCH] pasemi_mac: Enable L2 caching of packet headers
Enable settings to target l2 for the first few cachelines of the packet, since
we'll access them to get to the various headers.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
---
drivers/net/pasemi_mac.c | 5 ++++-
drivers/net/pasemi_mac.h | 8 ++++++++
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/net/pasemi_mac.c b/drivers/net/pasemi_mac.c
index be311e9404b4..46d5c0eef784 100644
--- a/drivers/net/pasemi_mac.c
+++ b/drivers/net/pasemi_mac.c
@@ -206,7 +206,7 @@ static int pasemi_mac_setup_rx_resources(struct net_device *dev)
PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 2));
write_dma_reg(mac, PAS_DMA_RXCHAN_CFG(chan_id),
- PAS_DMA_RXCHAN_CFG_HBU(1));
+ PAS_DMA_RXCHAN_CFG_HBU(2));
write_dma_reg(mac, PAS_DMA_RXINT_BASEL(mac->dma_if),
PAS_DMA_RXINT_BASEL_BRBL(__pa(ring->buffers)));
@@ -215,6 +215,9 @@ static int pasemi_mac_setup_rx_resources(struct net_device *dev)
PAS_DMA_RXINT_BASEU_BRBH(__pa(ring->buffers) >> 32) |
PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
+ write_dma_reg(mac, PAS_DMA_RXINT_CFG(mac->dma_if),
+ PAS_DMA_RXINT_CFG_DHL(2));
+
ring->next_to_fill = 0;
ring->next_to_clean = 0;
diff --git a/drivers/net/pasemi_mac.h b/drivers/net/pasemi_mac.h
index ef443640c768..fbbc17a31db7 100644
--- a/drivers/net/pasemi_mac.h
+++ b/drivers/net/pasemi_mac.h
@@ -219,6 +219,14 @@ enum {
#define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000
#define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000
#define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17
+#define PAS_DMA_RXINT_CFG(i) (0x204+(i)*_PAS_DMA_RXINT_STRIDE)
+#define PAS_DMA_RXINT_CFG_DHL_M 0x07000000
+#define PAS_DMA_RXINT_CFG_DHL_S 24
+#define PAS_DMA_RXINT_CFG_DHL(x) (((x) << PAS_DMA_RXINT_CFG_DHL_S) & \
+ PAS_DMA_RXINT_CFG_DHL_M)
+#define PAS_DMA_RXINT_CFG_WIF 0x00000002
+#define PAS_DMA_RXINT_CFG_WIL 0x00000001
+
#define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
#define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff
#define PAS_DMA_RXINT_INCR_INCR_S 0
--
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