From 60c5ea2dd981d929d873823433294b991d3e3cd8 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Fri, 4 May 2012 17:18:22 -0300 Subject: [PATCH] drm/i915: mask the video DIP frequency when changing it Better safe than sorry. Currently we never change the frequency and use the same for every infoframe type, so the only way to reproduce a bug would be with the BIOS doing something. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_hdmi.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 71e7af91f1b1..ce6e64dd00ff 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1711,6 +1711,7 @@ #define VIDEO_DIP_FREQ_ONCE (0 << 16) #define VIDEO_DIP_FREQ_VSYNC (1 << 16) #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) +#define VIDEO_DIP_FREQ_MASK (3 << 16) /* Panel power sequencing */ #define PP_STATUS 0x61200 diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 6c96bb54e967..4a4ee8b25f2f 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -164,6 +164,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder, } val |= intel_infoframe_enable(frame); + val &= ~VIDEO_DIP_FREQ_MASK; val |= intel_infoframe_frequency(frame); I915_WRITE(VIDEO_DIP_CTL, val); @@ -203,6 +204,7 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder, } val |= intel_infoframe_enable(frame); + val &= ~VIDEO_DIP_FREQ_MASK; val |= intel_infoframe_frequency(frame); I915_WRITE(reg, val); @@ -236,6 +238,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, } val |= intel_infoframe_enable(frame); + val &= ~VIDEO_DIP_FREQ_MASK; val |= intel_infoframe_frequency(frame); I915_WRITE(reg, val); -- GitLab