diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 973f2727d7033322658a7b444595d6e56be847da..9d871c7eeaeefa99f6fff680d192b3c9533d1ae2 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1565,6 +1565,9 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) case PSR_NO_SINK: seq_puts(m, "not supported by panel"); break; + case PSR_MODULE_PARAM: + seq_puts(m, "disabled by flag"); + break; case PSR_CRTC_NOT_ACTIVE: seq_puts(m, "crtc not active"); break; diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 0485f435eeeafe9238c9cdca1ebf902cbbfff755..b178a7ca129484a82602e0e15cb31d07d9f7d10e 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -118,6 +118,10 @@ module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); MODULE_PARM_DESC(i915_enable_ppgtt, "Enable PPGTT (default: true)"); +int i915_enable_psr __read_mostly = 0; +module_param_named(enable_psr, i915_enable_psr, int, 0600); +MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)"); + unsigned int i915_preliminary_hw_support __read_mostly = 0; module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600); MODULE_PARM_DESC(preliminary_hw_support, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 21d55f855d16236c0291e6fb56e984d424917789..36d1c806e092e3136472079424aa33f96bf3f1ac 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -596,6 +596,7 @@ struct i915_fbc { enum no_psr_reason { PSR_NO_SOURCE, /* Not supported on platform */ PSR_NO_SINK, /* Not supported by panel */ + PSR_MODULE_PARAM, PSR_CRTC_NOT_ACTIVE, PSR_PWR_WELL_ENABLED, PSR_NOT_TILED, @@ -1621,6 +1622,7 @@ extern int i915_enable_rc6 __read_mostly; extern int i915_enable_fbc __read_mostly; extern bool i915_enable_hangcheck __read_mostly; extern int i915_enable_ppgtt __read_mostly; +extern int i915_enable_psr __read_mostly; extern unsigned int i915_preliminary_hw_support __read_mostly; extern int i915_disable_power_well __read_mostly; extern int i915_enable_ips __read_mostly; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3ce1b872935e34751f1db190c0ede190213a75ab..6a4cdea76274af0427934544c3cdd7ff264d533d 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1521,6 +1521,12 @@ static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) return false; } + if (!i915_enable_psr) { + DRM_DEBUG_KMS("PSR disable by flag\n"); + dev_priv->no_psr_reason = PSR_MODULE_PARAM; + return false; + } + if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) { DRM_DEBUG_KMS("crtc not active for PSR\n"); dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;