Merge branch 'meklort/refactor-python' into 'master'

Initial refactor of kestrel code - will be used for versa adapter board changes.

See merge request kestrel-collaboration/kestrel-litex/litex-boards!7
parents 71724d67 b804285f
......@@ -178,22 +178,23 @@ _io = [
Subsignal("n", Pins("Y8")),
),
("i2c_bus1_master", 0,
("i2c_master", 1,
Subsignal("sda", Pins("D12"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
Subsignal("scl", Pins("B10"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
),
("i2c_bus2_master", 0,
("i2c_master", 2,
Subsignal("sda", Pins("C10"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
Subsignal("scl", Pins("A9"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
),
("i2c_bus3_master", 0,
Subsignal("sda", Pins("B17"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
Subsignal("scl", Pins("C17"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
),
# Not needed for Blackbird / Talos II / Sparrowhawk; save space on the Versa board ECP5 -45 device
# ("i2c_master", 3,
# Subsignal("sda", Pins("B17"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
# Subsignal("scl", Pins("C17"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
# ),
("i2c_bus4_master", 0,
("i2c_master", 4,
Subsignal("sda", Pins("B18"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
Subsignal("scl", Pins("A18"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
),
......
......@@ -195,7 +195,10 @@ class BaseSoC(SoCCore):
# Debug pad locator
debug2_pads = platform.request("debug_port_2")
lpc_debug_mirror_clock_pad = platform.request("lpc_debug_mirror_clock")
try:
lpc_debug_mirror_clock_pad = platform.request("lpc_debug_mirror_clock")
except:
lpc_debug_mirror_clock_pad = Signal()
# Host SPI Flash (Tercel core) -------------------------------------------------------------
if with_hostspiflash:
......@@ -269,49 +272,24 @@ class BaseSoC(SoCCore):
# I2C Masters ------------------------------------------------------------------------------
if with_i2c_masters:
i2cmaster1_pads = platform.request("i2c_bus1_master")
self.submodules.i2cmaster1 = OpenCoresI2CMaster(
platform = platform,
pads = i2cmaster1_pads,
clk_freq = sys_clk_freq)
self.add_csr("i2cmaster1")
i2cmaster1_size = 32
i2cmaster1_region = SoCRegion(origin=self.mem_map.get("i2cmaster1", None), size=i2cmaster1_size, cached=False)
self.bus.add_slave(name="i2cmaster1", slave=self.i2cmaster1.bus, region=i2cmaster1_region)
if with_i2c_masters:
i2cmaster2_pads = platform.request("i2c_bus2_master")
self.submodules.i2cmaster2 = OpenCoresI2CMaster(
platform = platform,
pads = i2cmaster2_pads,
clk_freq = sys_clk_freq)
self.add_csr("i2cmaster2")
i2cmaster2_size = 32
i2cmaster2_region = SoCRegion(origin=self.mem_map.get("i2cmaster2", None), size=i2cmaster2_size, cached=False)
self.bus.add_slave(name="i2cmaster2", slave=self.i2cmaster2.bus, region=i2cmaster2_region)
# Not needed for Blackbird / Talos II / Sparrowhawk; save space on the Versa board ECP5 -45 device
#if with_i2c_masters:
#i2cmaster3_pads = platform.request("i2c_bus3_master")
#self.submodules.i2cmaster3 = OpenCoresI2CMaster(
#platform = platform,
#pads = i2cmaster3_pads,
#clk_freq = sys_clk_freq)
#self.add_csr("i2cmaster3")
#i2cmaster3_size = 32
#i2cmaster3_region = SoCRegion(origin=self.mem_map.get("i2cmaster3", None), size=i2cmaster3_size, cached=False)
#self.bus.add_slave(name="i2cmaster3", slave=self.i2cmaster3.bus, region=i2cmaster3_region)
if with_i2c_masters:
i2cmaster4_pads = platform.request("i2c_bus4_master")
self.submodules.i2cmaster4 = OpenCoresI2CMaster(
platform = platform,
pads = i2cmaster4_pads,
clk_freq = sys_clk_freq)
self.add_csr("i2cmaster4")
i2cmaster4_size = 32
i2cmaster4_region = SoCRegion(origin=self.mem_map.get("i2cmaster4", None), size=i2cmaster4_size, cached=False)
self.bus.add_slave(name="i2cmaster4", slave=self.i2cmaster4.bus, region=i2cmaster4_region)
for i2c_master_id in range(0, 5):
i2c_master_pads = platform.request("i2c_master", i2c_master_id, True)
if not i2c_master_pads:
continue
master_name = "i2cmaster%d" % i2c_master_id
i2cmaster = OpenCoresI2CMaster(
platform = platform,
pads = i2c_master_pads,
clk_freq = sys_clk_freq)
setattr(self.submodules, master_name, i2cmaster)
self.add_csr(master_name)
i2cmaster_size = 32
i2cmaster_region = SoCRegion(origin=self.mem_map.get(master_name, None), size=i2cmaster_size, cached=False)
self.bus.add_slave(name=master_name, slave=i2cmaster.bus, region=i2cmaster_region)
if platform.request("i2c_master", None, True):
raise ValueError("Unhandled i2c_master found")
# SimpleRTC --------------------------------------------------------------------------------
if with_simple_rtc:
......
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