bootrom: Revup bootrom submodule

See merge request !1

- Add common routines for cpu0/cpu1
- Wrap CPU1 code in #ifdef I3CMASTER2_BASE in teh event that the FPGA was not build with the additioanl i2c master.

- Fix description for 64MB flash chips to be 512Mb not 512MB
- Add Support for the 128MB flash chips

Previously, back to back FSI transactions could happen before teh FSI state machine was complete.
This ensures that the FSI master does not ahve an active transaction before starting a new one.

This could result in logs such as:
access_fsi_mem(): address 0x002820, data: 0x00000000 sta: 0x41000001
access_fsi_mem(): address 0x002804, data: 0x00000000 sta: 0x12000000
vs
access_fsi_mem(): address 0x002820, data: 0x00000000 sta: 0x41000001
access_fsi_mem(): address 0x002804, data: 0x04c04000 sta: 0x41000001

As a result, the CPU often failed to start.

Major update
Verified to fully IPL attached Blackbird host to Petitboot shell using Versa ECP5

Do not attempt merged Flashed read/writes during 32-bit CPU accesses in non-merged mode
Split Kestrel SPI defines into dedicated header

Add initial integration of FSI core and FSI IPL firmware for Raptor Computing Systems POWER9 systems

Verified to properly start the IPL sequence on a Raptor Computing Systems Blackbird
with external LPC / IPMI bridge interface attached.

Cloned from litex-hub/fpga_101/lab004/firmware, and all
demo-specific display / LED test functionality removed.

Per the author, _florent_, on Freenode IRC 06/14/2020,
this basic code is provided without any copyright restrictions.