Commit 19e0696f authored by Evan Lojewski's avatar Evan Lojewski Committed by Raptor Engineering Development Team

build: Enable clang-formatting various source files.

parent 3a4dae15
Language: Cpp
AccessModifierOffset: -4
AlignAfterOpenBracket: Align
AlignConsecutiveAssignments: false
AlignConsecutiveDeclarations: false
AlignConsecutiveMacros: true
AlignEscapedNewlines: Right
AlignOperands: true
AlignTrailingComments: true
AllowAllParametersOfDeclarationOnNextLine: true
AllowShortBlocksOnASingleLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: None
AllowShortIfStatementsOnASingleLine: false
AllowShortLoopsOnASingleLine: false
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: MultiLine
BinPackArguments: true
BinPackParameters: true
BraceWrapping:
AfterCaseLabel: true
AfterClass: false
AfterControlStatement: true
AfterEnum: true
AfterFunction: true
AfterNamespace: false
AfterObjCDeclaration: true
AfterStruct: true
AfterUnion: true
AfterExternBlock: false
BeforeCatch: false
BeforeElse: true
IndentBraces: false
SplitEmptyFunction: true
SplitEmptyRecord: true
SplitEmptyNamespace: true
BreakBeforeBinaryOperators: None
BreakBeforeBraces: Custom
BreakBeforeInheritanceComma: false
BreakInheritanceList: BeforeColon
BreakBeforeTernaryOperators: true
BreakConstructorInitializersBeforeComma: true
BreakConstructorInitializers: AfterColon
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: true
ColumnLimit: 160
CommentPragmas: '^lint'
CompactNamespaces: false
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ConstructorInitializerIndentWidth: 4
ContinuationIndentWidth: 4
Cpp11BracedListStyle: false
DerivePointerAlignment: false
DisableFormat: false
ExperimentalAutoDetectBinPacking: false
FixNamespaceComments: true
ForEachMacros:
- foreach
- Q_FOREACH
- BOOST_FOREACH
IncludeBlocks: Regroup
IncludeCategories:
- Regex: '^"(llvm|llvm-c|clang|clang-c)/'
Priority: 2
- Regex: '^(<|"(gtest|gmock|isl|json)/)'
Priority: 3
- Regex: '.*'
Priority: 1
IncludeIsMainRegex: '(Test)?$'
IndentCaseLabels: true
IndentPPDirectives: None
IndentWidth: 4
IndentWrappedFunctionNames: false
JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: true
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: None
ObjCBinPackProtocolList: Auto
ObjCBlockIndentWidth: 2
ObjCSpaceAfterProperty: false
ObjCSpaceBeforeProtocolList: true
PenaltyBreakAssignment: 2
PenaltyBreakBeforeFirstCallParameter: 19
PenaltyBreakComment: 300
PenaltyBreakFirstLessLess: 120
PenaltyBreakString: 1000
PenaltyBreakTemplateDeclaration: 10
PenaltyExcessCharacter: 1000000
PenaltyReturnTypeOnItsOwnLine: 60
PointerAlignment: Right
ReflowComments: true
SortIncludes: true
SortUsingDeclarations: true
SpaceAfterCStyleCast: false
SpaceAfterTemplateKeyword: false
SpaceBeforeAssignmentOperators: true
SpaceBeforeCpp11BracedList: false
SpaceBeforeCtorInitializerColon: true
SpaceBeforeInheritanceColon: true
SpaceBeforeParens: ControlStatements
SpaceBeforeRangeBasedForLoopColon: true
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: false
SpacesInContainerLiterals: false
SpacesInCStyleCastParentheses: false
SpacesInParentheses: false
SpacesInSquareBrackets: false
Standard: Cpp11
TabWidth: 4
UseTab: Never
......@@ -84,12 +84,19 @@ add_definitions("-D__microwatt__")
add_subdirectory(bootrom/libbase)
ppc64le_add_executable(${PROJECT_NAME}
utility.c
utility.c utility.h
isr.c
main.c
fsi.c
opencores_i2c.c
fsi.c fsi.h
opencores_i2c.c opencores_i2c.h
aquila.h
ipmi_bt.h
micron_n25q_flash.h
tercel_spi.h
)
ppc64le_linker_script(${PROJECT_NAME} "${CMAKE_CURRENT_SOURCE_DIR}/linker.ld")
target_link_libraries(${PROJECT_NAME} PRIVATE libbase-nofloat)
target_compile_definitions(${PROJECT_NAME} PRIVATE "-DNO_FLINT") # Disable linting
format_target_sources(${PROJECT_NAME})
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......@@ -6,55 +6,60 @@
#ifndef _FSI_H
#define _FSI_H
typedef enum {
FSI_DATA_LENGTH_BYTE = 0,
FSI_DATA_LENGTH_HALFWORD = 1,
FSI_DATA_LENGTH_WORD = 2
#include <stdint.h>
typedef enum
{
FSI_DATA_LENGTH_BYTE = 0,
FSI_DATA_LENGTH_HALFWORD = 1,
FSI_DATA_LENGTH_WORD = 2
} fsi_data_length_t;
// Peripheral registers
#define FSI_MASTER_REG_DEVICE_ID_HIGH 0x0
#define FSI_MASTER_REG_DEVICE_ID_LOW 0x4
#define FSI_MASTER_REG_DEVICE_VERSION 0x8
#define FSI_MASTER_REG_SID_ADR 0xc
#define FSI_MASTER_REG_CONTROL 0x10
#define FSI_MASTER_REG_STATUS 0x14
#define FSI_MASTER_REG_TX_DATA 0x18
#define FSI_MASTER_REG_RX_DATA 0x1c
#define FSI_MASTER_REG_DMA_IRQ 0x20
#define FSI_MASTER_REG_DEVICE_ID_HIGH 0x0
#define FSI_MASTER_REG_DEVICE_ID_LOW 0x4
#define FSI_MASTER_REG_DEVICE_VERSION 0x8
#define FSI_MASTER_REG_SID_ADR 0xc
#define FSI_MASTER_REG_CONTROL 0x10
#define FSI_MASTER_REG_STATUS 0x14
#define FSI_MASTER_REG_TX_DATA 0x18
#define FSI_MASTER_REG_RX_DATA 0x1c
#define FSI_MASTER_REG_DMA_IRQ 0x20
#define FSI_MASTER_SID_SLAVE_ID_MASK 0x3
#define FSI_MASTER_SID_SLAVE_ID_SHIFT 29
#define FSI_MASTER_SID_ADDRESS_MASK 0x1fffff
#define FSI_MASTER_SID_ADDRESS_SHIFT 8
#define FSI_MASTER_SID_DATA_LENGTH_MASK 0x3
#define FSI_MASTER_SID_DATA_LENGTH_SHIFT 0
#define FSI_MASTER_SID_SLAVE_ID_MASK 0x3
#define FSI_MASTER_SID_SLAVE_ID_SHIFT 29
#define FSI_MASTER_SID_ADDRESS_MASK 0x1fffff
#define FSI_MASTER_SID_ADDRESS_SHIFT 8
#define FSI_MASTER_SID_DATA_LENGTH_MASK 0x3
#define FSI_MASTER_SID_DATA_LENGTH_SHIFT 0
#define FSI_MASTER_CTL_CMD_ISSUE_DELAY_MASK 0xff
#define FSI_MASTER_CTL_CMD_ISSUE_DELAY_SHIFT 8
#define FSI_MASTER_CTL_DATA_DIRECTION_MASK 0x1
#define FSI_MASTER_CTL_DATA_DIRECTION_SHIFT 1
#define FSI_MASTER_CTL_ENABLE_CRC_MASK 0x1
#define FSI_MASTER_CTL_ENABLE_CRC_SHIFT 17
#define FSI_MASTER_CTL_ENABLE_EER_MASK 0x1
#define FSI_MASTER_CTL_ENABLE_EER_SHIFT 16
#define FSI_MASTER_CTL_CYCLE_START_MASK 0x1
#define FSI_MASTER_CTL_CYCLE_START_SHIFT 0
#define FSI_MASTER_CTL_CMD_ISSUE_DELAY_MASK 0xff
#define FSI_MASTER_CTL_CMD_ISSUE_DELAY_SHIFT 8
#define FSI_MASTER_CTL_DATA_DIRECTION_MASK 0x1
#define FSI_MASTER_CTL_DATA_DIRECTION_SHIFT 1
#define FSI_MASTER_CTL_ENABLE_CRC_MASK 0x1
#define FSI_MASTER_CTL_ENABLE_CRC_SHIFT 17
#define FSI_MASTER_CTL_ENABLE_EER_MASK 0x1
#define FSI_MASTER_CTL_ENABLE_EER_SHIFT 16
#define FSI_MASTER_CTL_CYCLE_START_MASK 0x1
#define FSI_MASTER_CTL_CYCLE_START_SHIFT 0
#define FSI_MASTER_STAT_CYCLE_ERROR_MASK 0x7
#define FSI_MASTER_STAT_CYCLE_ERROR_SHIFT 8
#define FSI_MASTER_STAT_CYCLE_COMPLETE_MASK 0x1
#define FSI_MASTER_STAT_CYCLE_COMPLETE_SHIFT 0
#define FSI_MASTER_STAT_CYCLE_ERROR_MASK 0x7
#define FSI_MASTER_STAT_CYCLE_ERROR_SHIFT 8
#define FSI_MASTER_STAT_CYCLE_COMPLETE_MASK 0x1
#define FSI_MASTER_STAT_CYCLE_COMPLETE_SHIFT 0
#define FSI_DIRECTION_READ 0
#define FSI_DIRECTION_WRITE 1
#define FSI_DIRECTION_READ 0
#define FSI_DIRECTION_WRITE 1
static inline uint32_t read_openfsi_register(unsigned long base_address, uint8_t reg) {
return *((volatile uint32_t*)(base_address + reg));
static inline uint32_t read_openfsi_register(unsigned long base_address, uint8_t reg)
{
return *((volatile uint32_t *)(base_address + reg));
}
static inline void write_openfsi_register(unsigned long base_address, uint8_t reg, uint32_t data) {
*((volatile uint32_t*)(base_address + reg)) = data;
static inline void write_openfsi_register(unsigned long base_address, uint8_t reg, uint32_t data)
{
*((volatile uint32_t *)(base_address + reg)) = data;
}
int run_pre_ipl_fixups(void);
......
This diff is collapsed.
#include "aquila.h"
#include <generated/csr.h>
#include <generated/soc.h>
#include <irq.h>
#include <uart.h>
#include "aquila.h"
uint32_t irq_unhandled_vector = 0;
uint32_t irq_unhandled_source = 0;
uint8_t irq_unhandled_vector_valid = 0;
......@@ -17,64 +17,74 @@ void isr_dec(void);
void isr(uint64_t vec)
{
vec = vec & 0xFFF;
if (vec == 0x900)
{
// DEC interrupt
isr_dec();
return;
}
if (vec == 0x500)
{
// Read interrupt source
uint32_t xirr = xics_icp_readw(PPC_XICS_XIRR);
uint32_t irq_source = xirr & 0x00ffffff;
__attribute__((unused)) unsigned int irqs;
// Handle IPI interrupts separately
if (irq_source == 2) {
// IPI interrupt
xics_icp_writeb(PPC_XICS_MFRR, 0xff);
}
else if (irq_source == 0) {
// Unknown source, slently ignore...
}
else {
// External interrupt
irqs = irq_pending() & irq_getmask();
vec = vec & 0xFFF;
if (vec == 0x900)
{
// DEC interrupt
isr_dec();
return;
}
if (vec == 0x500)
{
// Read interrupt source
uint32_t xirr = xics_icp_readw(PPC_XICS_XIRR);
uint32_t irq_source = xirr & 0x00ffffff;
__attribute__((unused)) unsigned int irqs;
// Handle IPI interrupts separately
if (irq_source == 2)
{
// IPI interrupt
xics_icp_writeb(PPC_XICS_MFRR, 0xff);
}
else if (irq_source == 0)
{
// Unknown source, slently ignore...
}
else
{
// External interrupt
irqs = irq_pending() & irq_getmask();
#ifndef UART_POLLING
if (irqs & (1 << UART_INTERRUPT))
uart_isr();
if (irqs & (1 << UART_INTERRUPT))
{
uart_isr();
}
#endif
if (irqs & (1 << HOSTLPCSLAVE_INTERRUPT))
lpc_slave_isr();
if (irqs & (1 << HOSTLPCSLAVE_INTERRUPT))
{
lpc_slave_isr();
}
if (!irqs) {
irq_unhandled_source = irq_source;
irq_unhandled_source_valid = 1;
}
}
if (!irqs)
{
irq_unhandled_source = irq_source;
irq_unhandled_source_valid = 1;
}
}
// Clear interrupt
xics_icp_writew(PPC_XICS_XIRR, xirr);
// Clear interrupt
xics_icp_writew(PPC_XICS_XIRR, xirr);
return;
}
return;
}
irq_unhandled_vector = vec;
irq_unhandled_vector_valid = 1;
while (1);
irq_unhandled_vector = vec;
irq_unhandled_vector_valid = 1;
while (1)
;
}
void isr_dec(void)
{
// For now, just set DEC back to a large enough value to slow the flood of DEC-initiated timer interrupts
mtdec(0x000000000ffffff);
// For now, just set DEC back to a large enough value to slow the flood of
// DEC-initiated timer interrupts
mtdec(0x000000000ffffff);
}
#else
......
This diff is collapsed.
......@@ -3,30 +3,27 @@
// Released under the terms of the GPL v3
// See the LICENSE file for full details
uint32_t micron_n25q_spi_device_ids[] = {
0x20ba2010
};
uint32_t micron_n25q_spi_device_ids[] = { 0x20ba2010 };
const char* micron_n25q_spi_device_names[] = {
"Micron N25Q 512MB"
};
const char *micron_n25q_spi_device_names[] = { "Micron N25Q 512MB" };
#define MICRON_N25Q_SPI_FAST_READ_DUMMY_CLOCK_CYCLES 10
#define MICRON_N25Q_SPI_FAST_READ_DUMMY_CLOCK_CYCLES 10
#define MICRON_N25Q_SPI_3BA_SPI_READ_CMD 0x03
#define MICRON_N25Q_SPI_4BA_SPI_READ_CMD 0x13
#define MICRON_N25Q_SPI_3BA_SPI_READ_CMD 0x03
#define MICRON_N25Q_SPI_4BA_SPI_READ_CMD 0x13
// NOTE: QSPI mode unavailable for single read, use Write Disable command as plaecholder
#define MICRON_N25Q_SPI_3BA_QSPI_READ_CMD 0x04
#define MICRON_N25Q_SPI_4BA_QSPI_READ_CMD 0x04
#define MICRON_N25Q_SPI_3BA_QSPI_READ_CMD 0x04
#define MICRON_N25Q_SPI_4BA_QSPI_READ_CMD 0x04
#define MICRON_N25Q_SPI_3BA_SPI_FAST_READ_CMD 0x0b
#define MICRON_N25Q_SPI_4BA_SPI_FAST_READ_CMD 0x0c
#define MICRON_N25Q_SPI_3BA_QSPI_FAST_READ_CMD 0xeb
#define MICRON_N25Q_SPI_4BA_QSPI_FAST_READ_CMD 0xec
#define MICRON_N25Q_SPI_3BA_SPI_FAST_READ_CMD 0x0b
#define MICRON_N25Q_SPI_4BA_SPI_FAST_READ_CMD 0x0c
#define MICRON_N25Q_SPI_3BA_QSPI_FAST_READ_CMD 0xeb
#define MICRON_N25Q_SPI_4BA_QSPI_FAST_READ_CMD 0xec
// NOTE: The same command code is used for both QSPI 3BA and QSPI 4BA extended quad input writes, thus the device must be placed in either 3BA or 4BA mode prior to issuing PAGE PROGRAM
#define MICRON_N25Q_SPI_3BA_SPI_PAGE_PROGRAM_CMD 0x02
#define MICRON_N25Q_SPI_4BA_SPI_PAGE_PROGRAM_CMD 0x12
#define MICRON_N25Q_SPI_3BA_QSPI_PAGE_PROGRAM_CMD 0x38
#define MICRON_N25Q_SPI_4BA_QSPI_PAGE_PROGRAM_CMD 0x38
\ No newline at end of file
// NOTE: The same command code is used for both QSPI 3BA and QSPI 4BA extended quad input writes, thus the device must be placed in either 3BA or 4BA mode prior
// to issuing PAGE PROGRAM
#define MICRON_N25Q_SPI_3BA_SPI_PAGE_PROGRAM_CMD 0x02
#define MICRON_N25Q_SPI_4BA_SPI_PAGE_PROGRAM_CMD 0x12
#define MICRON_N25Q_SPI_3BA_QSPI_PAGE_PROGRAM_CMD 0x38
#define MICRON_N25Q_SPI_4BA_QSPI_PAGE_PROGRAM_CMD 0x38
\ No newline at end of file
This diff is collapsed.
......@@ -6,68 +6,70 @@
#ifndef _OPENCORES_I2C_H
#define _OPENCORES_I2C_H
#define OPENCORES_I2C_MASTER_DEVICE_ID_LOW 0x0
#define OPENCORES_I2C_MASTER_DEVICE_ID_HIGH 0x4
#define OPENCORES_I2C_MASTER_DEVICE_VERSION 0x8
#define OPENCORES_I2C_MASTER_PRESCALE_LOW 0x10
#define OPENCORES_I2C_MASTER_PRESCALE_HIGH 0x11
#define OPENCORES_I2C_MASTER_PRESCALE_CTL 0x12
#define OPENCORES_I2C_MASTER_TX_RX 0x13
#define OPENCORES_I2C_MASTER_CMD_STATUS 0x14
#include <stdint.h>
#define OPENCORES_I2C_DEVICE_ID_HIGH 0x4932434d
#define OPENCORES_I2C_DEVICE_ID_LOW 0x4f504e43
#define OPENCORES_I2C_MASTER_DEVICE_ID_LOW 0x0
#define OPENCORES_I2C_MASTER_DEVICE_ID_HIGH 0x4
#define OPENCORES_I2C_MASTER_DEVICE_VERSION 0x8
#define OPENCORES_I2C_MASTER_PRESCALE_LOW 0x10
#define OPENCORES_I2C_MASTER_PRESCALE_HIGH 0x11
#define OPENCORES_I2C_MASTER_PRESCALE_CTL 0x12
#define OPENCORES_I2C_MASTER_TX_RX 0x13
#define OPENCORES_I2C_MASTER_CMD_STATUS 0x14
#define OPENCORES_I2C_VERSION_MAJOR_MASK 0xffff
#define OPENCORES_I2C_VERSION_MAJOR_SHIFT 16
#define OPENCORES_I2C_VERSION_MINOR_MASK 0xff
#define OPENCORES_I2C_VERSION_MINOR_SHIFT 8
#define OPENCORES_I2C_VERSION_PATCH_MASK 0xff
#define OPENCORES_I2C_VERSION_PATCH_SHIFT 0
#define OPENCORES_I2C_DEVICE_ID_HIGH 0x4932434d
#define OPENCORES_I2C_DEVICE_ID_LOW 0x4f504e43
#define OPENCORES_I2C_MASTER_CTL_CORE_EN_MASK 0x1
#define OPENCORES_I2C_MASTER_CTL_CORE_EN_SHIFT 7
#define OPENCORES_I2C_MASTER_CTL_IRQ_EN_MASK 0x1
#define OPENCORES_I2C_MASTER_CTL_IRQ_EN_SHIFT 6
#define OPENCORES_I2C_VERSION_MAJOR_MASK 0xffff
#define OPENCORES_I2C_VERSION_MAJOR_SHIFT 16
#define OPENCORES_I2C_VERSION_MINOR_MASK 0xff
#define OPENCORES_I2C_VERSION_MINOR_SHIFT 8
#define OPENCORES_I2C_VERSION_PATCH_MASK 0xff
#define OPENCORES_I2C_VERSION_PATCH_SHIFT 0
#define OPENCORES_I2C_MASTER_CMD_STA_MASK 0x1
#define OPENCORES_I2C_MASTER_CMD_STA_SHIFT 7
#define OPENCORES_I2C_MASTER_CMD_STO_MASK 0x1
#define OPENCORES_I2C_MASTER_CMD_STO_SHIFT 6
#define OPENCORES_I2C_MASTER_CMD_RD_MASK 0x1
#define OPENCORES_I2C_MASTER_CMD_RD_SHIFT 5
#define OPENCORES_I2C_MASTER_CMD_WR_MASK 0x1
#define OPENCORES_I2C_MASTER_CMD_WR_SHIFT 4
#define OPENCORES_I2C_MASTER_CMD_ACK_MASK 0x0
#define OPENCORES_I2C_MASTER_CMD_ACK_SHIFT 3
#define OPENCORES_I2C_MASTER_CMD_NACK_MASK 0x1
#define OPENCORES_I2C_MASTER_CMD_NACK_SHIFT 3
#define OPENCORES_I2C_MASTER_CMD_IACK_MASK 0x1
#define OPENCORES_I2C_MASTER_CMD_IACK_SHIFT 0
#define OPENCORES_I2C_MASTER_CTL_CORE_EN_MASK 0x1
#define OPENCORES_I2C_MASTER_CTL_CORE_EN_SHIFT 7
#define OPENCORES_I2C_MASTER_CTL_IRQ_EN_MASK 0x1
#define OPENCORES_I2C_MASTER_CTL_IRQ_EN_SHIFT 6
#define OPENCORES_I2C_MASTER_STATUS_RXACK_MASK 0x1
#define OPENCORES_I2C_MASTER_STATUS_RXACK_SHIFT 7
#define OPENCORES_I2C_MASTER_STATUS_BUSY_MASK 0x1
#define OPENCORES_I2C_MASTER_STATUS_BUSY_SHIFT 6
#define OPENCORES_I2C_MASTER_STATUS_ARBL_MASK 0x1
#define OPENCORES_I2C_MASTER_STATUS_ARBL_SHIFT 5
#define OPENCORES_I2C_MASTER_STATUS_TIP_MASK 0x1
#define OPENCORES_I2C_MASTER_STATUS_TIP_SHIFT 1
#define OPENCORES_I2C_MASTER_STATUS_IRQP_MASK 0x1
#define OPENCORES_I2C_MASTER_STATUS_IRQP_SHIFT 0
#define OPENCORES_I2C_MASTER_CMD_STA_MASK 0x1
#define OPENCORES_I2C_MASTER_CMD_STA_SHIFT 7
#define OPENCORES_I2C_MASTER_CMD_STO_MASK 0x1
#define OPENCORES_I2C_MASTER_CMD_STO_SHIFT 6
#define OPENCORES_I2C_MASTER_CMD_RD_MASK 0x1
#define OPENCORES_I2C_MASTER_CMD_RD_SHIFT 5
#define OPENCORES_I2C_MASTER_CMD_WR_MASK 0x1
#define OPENCORES_I2C_MASTER_CMD_WR_SHIFT 4
#define OPENCORES_I2C_MASTER_CMD_ACK_MASK 0x0
#define OPENCORES_I2C_MASTER_CMD_ACK_SHIFT 3
#define OPENCORES_I2C_MASTER_CMD_NACK_MASK 0x1
#define OPENCORES_I2C_MASTER_CMD_NACK_SHIFT 3
#define OPENCORES_I2C_MASTER_CMD_IACK_MASK 0x1
#define OPENCORES_I2C_MASTER_CMD_IACK_SHIFT 0
#define OPENCORES_I2C_MASTER_TX_RX_WRITE_MASK 0x0
#define OPENCORES_I2C_MASTER_TX_RX_WRITE_SHIFT 0
#define OPENCORES_I2C_MASTER_TX_RX_READ_MASK 0x1
#define OPENCORES_I2C_MASTER_TX_RX_READ_SHIFT 0
#define OPENCORES_I2C_MASTER_STATUS_RXACK_MASK 0x1
#define OPENCORES_I2C_MASTER_STATUS_RXACK_SHIFT 7
#define OPENCORES_I2C_MASTER_STATUS_BUSY_MASK 0x1
#define OPENCORES_I2C_MASTER_STATUS_BUSY_SHIFT 6
#define OPENCORES_I2C_MASTER_STATUS_ARBL_MASK 0x1
#define OPENCORES_I2C_MASTER_STATUS_ARBL_SHIFT 5
#define OPENCORES_I2C_MASTER_STATUS_TIP_MASK 0x1
#define OPENCORES_I2C_MASTER_STATUS_TIP_SHIFT 1
#define OPENCORES_I2C_MASTER_STATUS_IRQP_MASK 0x1
#define OPENCORES_I2C_MASTER_STATUS_IRQP_SHIFT 0
#define I2C_MASTER_4_ADDR 0xc0010000L
#define I2C_MASTER_OPERATION_TIMEOUT_VALUE 10000
#define OPENCORES_I2C_MASTER_TX_RX_WRITE_MASK 0x0
#define OPENCORES_I2C_MASTER_TX_RX_WRITE_SHIFT 0
#define OPENCORES_I2C_MASTER_TX_RX_READ_MASK 0x1
#define OPENCORES_I2C_MASTER_TX_RX_READ_SHIFT 0
int initialize_i2c_master(uint8_t* base_address, int i2c_bus_frequency);
int write_i2c_data(uint8_t* base_address, uint8_t slave_address, uint8_t* data, int data_length, uint8_t send_stop_signal);
int read_i2c_data(uint8_t* base_address, uint8_t slave_address, uint8_t* data, int* data_length, int max_data_length, uint8_t send_stop_signal);
uint8_t i2c_read_register_byte(uint8_t* base_address, uint8_t slave_address, uint8_t slave_register, int* error);
int i2c_write_register_byte(uint8_t* base_address, uint8_t slave_address, uint8_t slave_register, uint8_t data);
#define I2C_MASTER_4_ADDR 0xc0010000L
#define I2C_MASTER_OPERATION_TIMEOUT_VALUE 10000
#endif // _OPENCORES_I2C_H
\ No newline at end of file
int initialize_i2c_master(uint8_t *base_address, int i2c_bus_frequency);
int write_i2c_data(uint8_t *base_address, uint8_t slave_address, uint8_t *data, int data_length, uint8_t send_stop_signal);
int read_i2c_data(uint8_t *base_address, uint8_t slave_address, uint8_t *data, int *data_length, int max_data_length, uint8_t send_stop_signal);
uint8_t i2c_read_register_byte(uint8_t *base_address, uint8_t slave_address, uint8_t slave_register, int *error);
int i2c_write_register_byte(uint8_t *base_address, uint8_t slave_address, uint8_t slave_register, uint8_t data);
#endif // _OPENCORES_I2C_H
......@@ -3,73 +3,75 @@
// Released under the terms of the GPL v3
// See the LICENSE file for full details
#define TERCEL_SPI_REG_DEVICE_ID_HIGH 0x0
#define TERCEL_SPI_REG_DEVICE_ID_LOW 0x4
#define TERCEL_SPI_REG_DEVICE_VERSION 0x8
#define TERCEL_SPI_REG_SYS_CLK_FREQ 0xc
#define TERCEL_SPI_REG_SYS_PHY_CFG1 0x10
#define TERCEL_SPI_REG_SYS_FLASH_CFG1 0x14
#define TERCEL_SPI_REG_SYS_FLASH_CFG2 0x18
#define TERCEL_SPI_REG_SYS_FLASH_CFG3 0x1c
#define TERCEL_SPI_REG_SYS_FLASH_CFG4 0x20
#define TERCEL_SPI_REG_SYS_FLASH_CFG5 0x24
#define TERCEL_SPI_REG_SYS_CORE_CTL1 0x28
#define TERCEL_SPI_REG_SYS_CORE_DATA1 0x2c
#define TERCEL_SPI_REG_DEVICE_ID_HIGH 0x0
#define TERCEL_SPI_REG_DEVICE_ID_LOW 0x4
#define TERCEL_SPI_REG_DEVICE_VERSION 0x8
#define TERCEL_SPI_REG_SYS_CLK_FREQ 0xc
#define TERCEL_SPI_REG_SYS_PHY_CFG1 0x10
#define TERCEL_SPI_REG_SYS_FLASH_CFG1 0x14
#define TERCEL_SPI_REG_SYS_FLASH_CFG2 0x18
#define TERCEL_SPI_REG_SYS_FLASH_CFG3 0x1c
#define TERCEL_SPI_REG_SYS_FLASH_CFG4 0x20
#define TERCEL_SPI_REG_SYS_FLASH_CFG5 0x24
#define TERCEL_SPI_REG_SYS_CORE_CTL1 0x28
#define TERCEL_SPI_REG_SYS_CORE_DATA1 0x2c
#define TERCEL_SPI_DEVICE_ID_HIGH 0x7c525054
#define TERCEL_SPI_DEVICE_ID_LOW 0x5350494d
#define TERCEL_SPI_DEVICE_ID_HIGH 0x7c525054
#define TERCEL_SPI_DEVICE_ID_LOW 0x5350494d
#define TERCEL_SPI_VERSION_MAJOR_MASK 0xffff
#define TERCEL_SPI_VERSION_MAJOR_SHIFT 16
#define TERCEL_SPI_VERSION_MINOR_MASK 0xff
#define TERCEL_SPI_VERSION_MINOR_SHIFT 8
#define TERCEL_SPI_VERSION_PATCH_MASK 0xff
#define TERCEL_SPI_VERSION_PATCH_SHIFT 0
#define TERCEL_SPI_VERSION_MAJOR_MASK 0xffff
#define TERCEL_SPI_VERSION_MAJOR_SHIFT 16
#define TERCEL_SPI_VERSION_MINOR_MASK 0xff
#define TERCEL_SPI_VERSION_MINOR_SHIFT 8
#define TERCEL_SPI_VERSION_PATCH_MASK 0xff
#define TERCEL_SPI_VERSION_PATCH_SHIFT 0
#define TERCEL_SPI_ENABLE_USER_MODE_MASK 0x1
#define TERCEL_SPI_ENABLE_USER_MODE_SHIFT 0x0
#define TERCEL_SPI_PHY_DUMMY_CYCLES_MASK 0xff
#define TERCEL_SPI_PHY_DUMMY_CYCLES_SHIFT 8
#define TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK 0xff
#define TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT 0
#define TERCEL_SPI_PHY_IO_TYPE_MASK 0x3
#define TERCEL_SPI_PHY_IO_TYPE_SHIFT 16
#define TERCEL_SPI_PHY_4BA_ENABLE_MASK 0x1
#define TERCEL_SPI_PHY_4BA_ENABLE_SHIFT 18
#define TERCEL_SPI_PHY_FAST_READ_ENABLE_MASK 0x1
#define TERCEL_SPI_PHY_FAST_READ_ENABLE_SHIFT 19
#define TERCEL_SPI_PHY_QSPI_EXT_READ_EN_MASK 0x1
#define TERCEL_SPI_PHY_QSPI_EXT_READ_EN_SHIFT 20
#define TERCEL_SPI_PHY_QSPI_EXT_WRITE_EN_MASK 0x1
#define TERCEL_SPI_PHY_QSPI_EXT_WRITE_EN_SHIFT 21
#define TERCEL_SPI_PHY_CS_EXTRA_IDLE_CYC_MASK 0xff
#define TERCEL_SPI_PHY_CS_EXTRA_IDLE_CYC_SHIFT 24
#define TERCEL_SPI_FLASH_EN_MULTCYC_WRITE_MASK 0x1
#define TERCEL_SPI_FLASH_EN_MULTCYC_WRITE_SHIFT 1
#define TERCEL_SPI_FLASH_EN_MULTCYC_READ_MASK 0x1
#define TERCEL_SPI_FLASH_EN_MULTCYC_READ_SHIFT 0
#define TERCEL_SPI_FLASH_CS_EN_LIMIT_CYC_MASK 0xffffffff
#define TERCEL_SPI_FLASH_CS_EN_LIMIT_CYC_SHIFT 0
#define TERCEL_SPI_ENABLE_USER_MODE_MASK 0x1
#define TERCEL_SPI_ENABLE_USER_MODE_SHIFT 0x0
#define TERCEL_SPI_PHY_DUMMY_CYCLES_MASK 0xff
#define TERCEL_SPI_PHY_DUMMY_CYCLES_SHIFT 8
#define TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK 0xff
#define TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT 0
#define TERCEL_SPI_PHY_IO_TYPE_MASK 0x3
#define TERCEL_SPI_PHY_IO_TYPE_SHIFT 16
#define TERCEL_SPI_PHY_4BA_ENABLE_MASK 0x1
#define TERCEL_SPI_PHY_4BA_ENABLE_SHIFT 18
#define TERCEL_SPI_PHY_FAST_READ_ENABLE_MASK 0x1
#define TERCEL_SPI_PHY_FAST_READ_ENABLE_SHIFT 19
#define TERCEL_SPI_PHY_QSPI_EXT_READ_EN_MASK 0x1
#define TERCEL_SPI_PHY_QSPI_EXT_READ_EN_SHIFT 20
#define TERCEL_SPI_PHY_QSPI_EXT_WRITE_EN_MASK 0x1
#define TERCEL_SPI_PHY_QSPI_EXT_WRITE_EN_SHIFT 21
#define TERCEL_SPI_PHY_CS_EXTRA_IDLE_CYC_MASK 0xff
#define TERCEL_SPI_PHY_CS_EXTRA_IDLE_CYC_SHIFT 24
#define TERCEL_SPI_FLASH_EN_MULTCYC_WRITE_MASK 0x1
#define TERCEL_SPI_FLASH_EN_MULTCYC_WRITE_SHIFT 1
#define TERCEL_SPI_FLASH_EN_MULTCYC_READ_MASK 0x1
#define TERCEL_SPI_FLASH_EN_MULTCYC_READ_SHIFT 0
#define TERCEL_SPI_FLASH_CS_EN_LIMIT_CYC_MASK 0xffffffff
#define TERCEL_SPI_FLASH_CS_EN_LIMIT_CYC_SHIFT 0
#define TERCEL_SPI_3BA_SPI_CMD_MASK 0xff
#define TERCEL_SPI_3BA_SPI_CMD_SHIFT 0
#define TERCEL_SPI_4BA_SPI_CMD_MASK 0xff
#define TERCEL_SPI_4BA_SPI_CMD_SHIFT 8
#define TERCEL_SPI_3BA_QSPI_CMD_MASK 0xff
#define TERCEL_SPI_3BA_QSPI_CMD_SHIFT 16
#define TERCEL_SPI_4BA_QSPI_CMD_MASK 0xff
#define TERCEL_SPI_4BA_QSPI_CMD_SHIFT 24
#define TERCEL_SPI_3BA_SPI_CMD_MASK 0xff
#define TERCEL_SPI_3BA_SPI_CMD_SHIFT 0
#define TERCEL_SPI_4BA_SPI_CMD_MASK 0xff
#define TERCEL_SPI_4BA_SPI_CMD_SHIFT 8
#define TERCEL_SPI_3BA_QSPI_CMD_MASK 0xff
#define TERCEL_SPI_3BA_QSPI_CMD_SHIFT 16
#define TERCEL_SPI_4BA_QSPI_CMD_MASK 0xff
#define TERCEL_SPI_4BA_QSPI_CMD_SHIFT 24
#define TERCEL_SPI_PHY_IO_TYPE_SINGLE 0x0
#define TERCEL_SPI_PHY_IO_TYPE_QUAD 0x2
#define TERCEL_SPI_PHY_IO_TYPE_SINGLE 0x0
#define TERCEL_SPI_PHY_IO_TYPE_QUAD 0x2
#define TERCEL_SPI_PHY_3BA_MODE 0x0
#define TERCEL_SPI_PHY_4BA_MODE 0x1
#define TERCEL_SPI_PHY_3BA_MODE 0x0
#define TERCEL_SPI_PHY_4BA_MODE 0x1
static inline uint32_t read_tercel_register(unsigned long base_address, uint8_t reg) {
return *((volatile uint32_t*)(base_address + reg));
static inline uint32_t read_tercel_register(unsigned long base_address, uint8_t reg)
{
return *((volatile uint32_t *)(base_address + reg));
}
static inline void write_tercel_register(unsigned long base_address, uint8_t reg, uint32_t data) {
*((volatile uint32_t*)(base_address + reg)) = data;
static inline void write_tercel_register(unsigned long base_address, uint8_t reg, uint32_t data)
{
*((volatile uint32_t *)(base_address + reg)) = data;
}
\ No newline at end of file
......@@ -3,12 +3,11 @@
// Released under the terms of the GPL v3
// See the LICENSE file for full details
#include <stdio.h>
#include <generated/soc.h>
#include <limits.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <limits.h>
#include <generated/soc.h>
#define TICKS_PER_US (CONFIG_CLOCK_FREQUENCY / 1000000LL)
......@@ -16,41 +15,43 @@
static __inline__ unsigned long long rdtsc(void)
{
unsigned long long int tsc;
unsigned long int high;
unsigned long int low;
unsigned long int scratch;
__asm__ volatile(
"0: \n"
"\tmftbu %0 \n"
"\tmftb %1 \n"
"\tmftbu %2 \n"
"\tcmpw %2,%0 \n"
"\tbne 0b \n"
: "=r"(high), "=r"(low), "=r"(scratch)
);
tsc = high << 32;
tsc |= low;
return tsc;
unsigned long long int tsc;
unsigned long int high;
unsigned long int low;
unsigned long int scratch;
__asm__ volatile("0: \n"
"\tmftbu %0 \n"
"\tmftb %1 \n"
"\tmftbu %2 \n"
"\tcmpw %2,%0 \n"
"\tbne 0b \n"
: "=r"(high), "=r"(low), "=r"(scratch));
tsc = high << 32;
tsc |= low;
return tsc;
}
void usleep(int usecs) {
unsigned long long start_tsc;
unsigned long long current_tsc;
unsigned long long offset;
offset = 0;
start_tsc = rdtsc();