From 7e2c079367fb2b9eb298b51a102ab40a70e79332 Mon Sep 17 00:00:00 2001
From: Peter Stuge <peter@stuge.se>
Date: Sun, 29 Jun 2008 01:30:41 +0000
Subject: [PATCH] Fix ICH7 non-SPI that broke in r3393
r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back
to 0 when BOOT BIOS Straps indicate something else than SPI.
Also fixes a build error in ichspi.c with gcc 4.2.2.
Corresponding to flashrom svn r280 and coreboot v2 svn r3395.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
---
chipset_enable.c | 2 ++
ichspi.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/chipset_enable.c b/chipset_enable.c
index d1ab964..dc6d8bc 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -212,6 +212,8 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsign
bbs = (gcs >> 10) & 0x3;
printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs,
(bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI"));
+ if (bbs >= 2)
+ ich7_detected = 0;
buc = *(volatile uint8_t *)(rcrb + 0x3414);
printf_debug("Top Swap : %s\n", (buc & 1)?"enabled (A16 inverted)":"not enabled");
diff --git a/ichspi.c b/ichspi.c
index d6c0157..b6b0f36 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -229,7 +229,7 @@ static int ich7_run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
{
int write_cmd = 0;
int timeout;
- uint32_t temp32;
+ uint32_t temp32 = 0;
uint16_t temp16;
uint32_t a;
--
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