Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
A
abc
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
Analytics
Analytics
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Commits
Issue Boards
Open sidebar
Kestrel Collaboration
Kestrel Tooling
abc
Repository
f9af41ba1bb6dff04e888c285052a9e1ec6d6456
Switch branch/tag
abc
src
base
io
io.c
Find file
Blame
History
Permalink
Adding an option to write Verilog with LUT instances.
· f9af41ba
Alan Mishchenko
authored
Oct 31, 2020
f9af41ba
io.c
110 KB
Edit
Web IDE
Replace io.c
×
Attach a file by drag & drop or
click to upload
Commit message
Replace io.c
Replace file
Cancel
A new branch will be created in your fork and a new merge request will be started.
