Expand the reg map to include space for 64-bit time stamps (not implemented)

This change just adds empty register slots for 64-bit time stamps in the relevant locations.

pythondata_peripheral_simplertc/rtl/simple_rtc.v

@@ -5,7 +5,28 @@
 
 // Stop LiteX silently ignoring net naming / missing register errors
 `default_nettype none
-
+//
+//register as words (32-bits):
+// Addr Acc     Index   Description
+// 0x00 RO      0:      dev ID low word
+// 0x04 RO      1:      dev ID hi word
+// 0x08 RO      2:      dev version
+// 0x0c RW      3:      cfg/strobe
+// 0x10 RW      4:      Set time lo
+// 0x14 RW      5:      Set time hi          # unimplemented
+// 0x18 RO      6:      current time lo
+// 0x1c RO      7:      current time hi      # unimplemented
+//
+// Addr:        lower byte of the memory address
+// Acc:         Access type. RO = read-only register (write are ignored), RW = read/write register.
+// Index:       Index, when access as a uint32_t *.
+// Description: Description/comments about the register.
+//
+// Brief usage description:
+// setting set time has no effect until cfg/strobe has bit zero set,
+// setting bit 1 of cfg/strobe will strobe the rtc and the time value
+// loaded into set time will be applied
+//
 module simple_rtc_wishbone #(
 		parameter BASE_CLOCK_FREQUENCY_KHZ = 1000
 	)
@@ -85,7 +106,9 @@ module simple_rtc_wishbone #(
 								8: mmio_cfg_space_tx_buffer = device_version;
 								12: mmio_cfg_space_tx_buffer = control_reg1;
 								16: mmio_cfg_space_tx_buffer = control_reg2;
-								20: mmio_cfg_space_tx_buffer = status_reg1;
+								//20: Reserved address space for control_reg2/hi word
+								24: mmio_cfg_space_tx_buffer = status_reg1;
+								//'28: Reserved Address space for current time hi word
 								default: mmio_cfg_space_tx_buffer = 0;
 							endcase
 
@@ -105,6 +128,7 @@ module simple_rtc_wishbone #(
 								// Device ID / version registers cannot be written, don't even try...
 								12: mmio_cfg_space_rx_buffer = control_reg1;
 								16: mmio_cfg_space_rx_buffer = control_reg2;
+								//20: Reserved for control reg 2 hi word
 								// Status registers cannot be written, don't even try...
 								default: mmio_cfg_space_rx_buffer = 0;
 							endcase
@@ -125,6 +149,7 @@ module simple_rtc_wishbone #(
 							case ({mmio_buffer_address_reg[7:2], 2'b00})
 								12: control_reg1 <= mmio_cfg_space_rx_buffer;
 								16: control_reg2 <= mmio_cfg_space_rx_buffer;
+								//20: Reserved for control reg 2 hi word
 							endcase
 
 							// Signal transfer complete