WIP -- get it to sort of fit...

e2281162 · Raptor Engineering Development Team · f9807b6d · e2281162
Commit e2281162 authored Jul 02, 2020 by Raptor Engineering Development Team
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pythondata_cpu_microwatt/vhdl/core.vhdl pythondata_cpu_microwatt/vhdl/core.vhdl +2 -2

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--- a/pythondata_cpu_microwatt/vhdl/core.vhdl
+++ b/pythondata_cpu_microwatt/vhdl/core.vhdl
@@ -201,7 +201,7 @@ begin
        generic map(
            SIM => SIM,
            LINE_SIZE => 64,
-            NUM_LINES => 64,
+            NUM_LINES => 2,
 	    NUM_WAYS => 2
            )
        port map(
@@ -343,7 +343,7 @@ begin
    dcache_0: entity work.dcache
        generic map(
            LINE_SIZE => 64,
-            NUM_LINES => 64,
+            NUM_LINES => 2,
 	    NUM_WAYS => 2
            )
        port map (