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pythondata-cpu-microwatt
Commit 5dc325fe authored by LiteX's avatar LiteX Committed by Travis CI User
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Merge commit '57604c1a'

parents 382943b6 57604c1a
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Showing with 24428 additions and 24138 deletions
pythondata_cpu_microwatt/vhdl/Makefile
View file @ 5dc325fe
......@@ -55,8 +55,9 @@ soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_
spi_rxtx.vhdl spi_flash_ctrl.vhdl
soc_sim_files = $(soc_files) sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl \
sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl
soc_sim_files = $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \
sim_16550_uart.vhdl
soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
sim_jtag_socket_c.c
......
pythondata_cpu_microwatt/vhdl/common.vhdl
View file @ 5dc325fe
......@@ -27,6 +27,7 @@ package common is
constant SPR_DSISR : spr_num_t := 18;
constant SPR_DAR : spr_num_t := 19;
constant SPR_TB : spr_num_t := 268;
constant SPR_TBU : spr_num_t := 269;
constant SPR_DEC : spr_num_t := 22;
constant SPR_SRR0 : spr_num_t := 26;
constant SPR_SRR1 : spr_num_t := 27;
......
pythondata_cpu_microwatt/vhdl/execute1.vhdl
View file @ 5dc325fe
......@@ -752,6 +752,9 @@ begin
case decode_spr_num(e_in.insn) is
when SPR_TB =>
spr_val := ctrl.tb;
when SPR_TBU =>
spr_val(63 downto 32) := (others => '0');
spr_val(31 downto 0) := ctrl.tb(63 downto 32);
when SPR_DEC =>
spr_val := ctrl.dec;
when 724 => -- LOG_ADDR SPR
......
pythondata_cpu_microwatt/vhdl/fpga/arty_a7.xdc
View file @ 5dc325fe
......@@ -4,7 +4,7 @@
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ext_rst }];
set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ext_rst_n }];
set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }];
set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }];
......@@ -13,10 +13,10 @@ set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_mai
# Pmod Header JC: UART (bottom)
################################################################################
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }];
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }];
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }];
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }];
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }];
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }];
set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }];
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }];
################################################################################
# RGB LEDs
......@@ -26,6 +26,15 @@ set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }
set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }];
set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }];
################################################################################
# Normal LEDs
################################################################################
set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { led4 }];
set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { led5 }];
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { led6 }];
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { led7 }];
################################################################################
# SPI Flash
################################################################################
......@@ -41,6 +50,85 @@ set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { spi_flas
set_property IOB true [get_cells -hierarchical -filter {NAME =~*/spi_rxtx/*sck_1*}]
set_property IOB true [get_cells -hierarchical -filter {NAME =~*/spi_rxtx/input_delay_1.dat_i_l*}]
################################################################################
# Ethernet (generated by LiteX)
################################################################################
# eth_ref_clk:0
set_property LOC G18 [get_ports {eth_ref_clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_ref_clk}]
# eth_clocks:0.tx
set_property LOC H16 [get_ports {eth_clocks_tx}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_tx}]
# eth_clocks:0.rx
set_property LOC F15 [get_ports {eth_clocks_rx}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_rx}]
# eth:0.rst_n
set_property LOC C16 [get_ports {eth_rst_n}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rst_n}]
# eth:0.mdio
set_property LOC K13 [get_ports {eth_mdio}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdio}]
# eth:0.mdc
set_property LOC F16 [get_ports {eth_mdc}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdc}]
# eth:0.rx_dv
set_property LOC G16 [get_ports {eth_rx_dv}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_dv}]
# eth:0.rx_er
set_property LOC C17 [get_ports {eth_rx_er}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_er}]
# eth:0.rx_data
set_property LOC D18 [get_ports {eth_rx_data[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[0]}]
# eth:0.rx_data
set_property LOC E17 [get_ports {eth_rx_data[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[1]}]
# eth:0.rx_data
set_property LOC E18 [get_ports {eth_rx_data[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[2]}]
# eth:0.rx_data
set_property LOC G17 [get_ports {eth_rx_data[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[3]}]
# eth:0.tx_en
set_property LOC H15 [get_ports {eth_tx_en}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_en}]
# eth:0.tx_data
set_property LOC H14 [get_ports {eth_tx_data[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[0]}]
# eth:0.tx_data
set_property LOC J14 [get_ports {eth_tx_data[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[1]}]
# eth:0.tx_data
set_property LOC J13 [get_ports {eth_tx_data[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[2]}]
# eth:0.tx_data
set_property LOC H17 [get_ports {eth_tx_data[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[3]}]
# eth:0.col
set_property LOC D17 [get_ports {eth_col}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_col}]
# eth:0.crs
set_property LOC G14 [get_ports {eth_crs}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_crs}]
################################################################################
# DRAM (generated by LiteX)
......@@ -326,10 +414,22 @@ set_property CONFIG_MODE SPIx4 [current_design]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }];
create_clock -name eth_rx_clk -period 40.0 [get_ports { eth_clocks_rx }]
create_clock -name eth_tx_clk -period 40.0 [get_ports { eth_clocks_tx }]
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets system_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_clocks_rx]] -asynchronous
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets system_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_clocks_tx]] -asynchronous
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets eth_clocks_rx]] -group [get_clocks -include_generated_clocks -of [get_nets eth_clocks_tx]] -asynchronous
################################################################################
# False path constraints (from LiteX as they relate to LiteDRAM)
# False path constraints (from LiteX as they relate to LiteDRAM and LiteEth)
################################################################################
set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}]
set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]
pythondata_cpu_microwatt/vhdl/fpga/top-generic.vhdl
View file @ 5dc325fe
......@@ -11,7 +11,8 @@ entity toplevel is
RESET_LOW : boolean := true;
CLK_INPUT : positive := 100000000;
CLK_FREQUENCY : positive := 100000000;
DISABLE_FLATTEN_CORE : boolean := false
DISABLE_FLATTEN_CORE : boolean := false;
UART_IS_16550 : boolean := true
);
port(
ext_clk : in std_ulogic;
......@@ -67,7 +68,8 @@ begin
RAM_INIT_FILE => RAM_INIT_FILE,
SIM => false,
CLK_FREQ => CLK_FREQUENCY,
DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE
DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
UART0_IS_16550 => UART_IS_16550
)
port map (
system_clk => system_clk,
......
pythondata_cpu_microwatt/vhdl/fpga/top-nexys-video.vhdl
View file @ 5dc325fe
......@@ -19,7 +19,8 @@ entity toplevel is
DISABLE_FLATTEN_CORE : boolean := false;
SPI_FLASH_OFFSET : integer := 10485760;
SPI_FLASH_DEF_CKDV : natural := 1;
SPI_FLASH_DEF_QUAD : boolean := true
SPI_FLASH_DEF_QUAD : boolean := true;
UART_IS_16550 : boolean := true;
);
port(
ext_clk : in std_ulogic;
......@@ -126,7 +127,8 @@ begin
SPI_FLASH_DLINES => 4,
SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD
SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
UART0_IS_16550 => UART_IS_16550
)
port map (
-- System signals
......
pythondata_cpu_microwatt/vhdl/hello_world/hello_world.c
View file @ 5dc325fe
......@@ -7,7 +7,7 @@
int main(void)
{
potato_uart_init();
console_init();
puts(HELLO_WORLD);
......
pythondata_cpu_microwatt/vhdl/hello_world/hello_world.hex
View file @ 5dc325fe
......@@ -514,73 +514,118 @@ e8010010ebc1fff0
7c0803a6ebe1fff8
3c4000014e800020
7c0802a63842a000
3fe2fffffbe1fff8
f80100103bff7240
48000051f821ffd1
7fe3fb7860000000
60000000480001d5
7fe3fb787c641b78
600000004800017d
60000000480000ed
480001295463063e
f821ffe1f8010010
60000000480001dd
386373a83c62ffff
6000000048000141
600000004800002d
480000a95463063e
4bffffec60000000
0100000000000000
3c40000100000180
3d20c0003842a000
6129200060000000
f922800079290020
612900203d20c000
7c0004ac79290020
3d40001c7d204eea
7d295392614a2000
394a0018e9428000
7c0004ac3929ffff
4e8000207d2057ea
0000000000000000
3c40000100000000
3c40000100000080
600000003842a000
394000ffe9228000
7c0004ac39290020
4e8000207d404fea
6000000039228000
8929000039428008
419e00302f890000
39290014e92a0000
7d204eaa7c0004ac
4182ffec71290001
7c0004ace86a0000
5463063e7c601eaa
e92a00004e800020
7c0004ac39290010
712900017d204eea
e86a00004082ffec
7c0004ac38630008
4bffffd07c601eea
0000000000000000
3c40000100000000
600000003842a000
39400000e9228000
7c0004ac39290020
4e8000207d404fea
6000000039228000
8929000039428008
419e002c2f890000
39290014e92a0000
7d204eaa7c0004ac
4182ffec71290020
7c0004ace92a0000
4e8000207c604faa
39290010e92a0000
7d204eea7c0004ac
4082ffec71290008
e94a00005469063e
7d2057ea7c0004ac
000000004e800020
0000000000000000
3842a0003c400001
fbc1fff07c0802a6
3bc3fffffbe1fff8
f821ffd1f8010010
2fbf00008ffe0001
38210030409e0010
4bfffe5c38600000
409e000c2b9f000a
4bffff413860000d
4bffff397fe3fb78
000000004bffffd0
0000028001000000
7d4348ae39200000
409e000c2f8a0000
4e8000207d234b78
4bffffe839290001
0000000000000000
3c40000100000000
600000003842a000
39290010e9228000
3d20c0003842a000
7929002061290020
7d204eea7c0004ac
4082ffe871290001
38630008e8628000
7c601eea7c0004ac
4e8000205463063e
792906003d00c000
7908002061080008
7d0046ea7c0004ac
3940000071080020
3d40c00041820018
794a0020614a0040
7d4056ea7c0004ac
600000003d00c000
38e2800060000000
7908002061082000
3d00001cf9028008
7d29439261082000
79080fc37948f804
3940000141820080
6108200c3d00c000
7908002099470000
7c0004ac3940ff80
e94280087d4047aa
7d2057aa7c0004ac
7929c202e9428008
7c0004ac394a0004
e92280087d2057aa
3929000c39400003
7d404faa7c0004ac
39290010e9228008
7d404faa7c0004ac
39400007e9228008
7c0004ac39290008
4e8000207d404faa
990700003d40c000
614a20183929ffff
7c0004ac794a0020
4e8000207d2057ea
0000000000000000
3c40000100000000
600000003842a000
39290010e9228000
7d204eea7c0004ac
4082ffe871290008
7c0004ace9228000
2ea4000039228000
2f89000089290000
e922800860000000
41960024419e0030
2fa3000039400002
614a0001419e0008
7c0004ac39290004
4e8000207d404faa
4bffffe039400000
6063000241960008
7c0004ac39290020
4e8000207c604fea
0000000000000000
3c40000100000000
7c0802a63842a000
fbe1fff8fbc1fff0
7c7f1b787fc32214
f821ffd1f8010010
409e000c7fbff040
4bfffe0c38210030
3bff0001887f0000
4bffffe44bffff8d
0100000000000000
3920000000000280
2f8a00007d4348ae
7d234b78409e000c
392900014e800020
000000004bffffe8
0000000000000000
6f57206f6c6c6548
0000000a0d646c72
000000000a646c72
pythondata_cpu_microwatt/vhdl/include/console.h
View file @ 5dc325fe
#include <stddef.h>
void potato_uart_init(void);
void potato_uart_irq_en(void);
void potato_uart_irq_dis(void);
void console_init(void);
void console_set_irq_en(bool rx_irq, bool tx_irq);
int getchar(void);
int putchar(int c);
int puts(const char *str);
......
pythondata_cpu_microwatt/vhdl/include/microwatt_soc.h
View file @ 5dc325fe
......@@ -15,6 +15,8 @@
#define XICS_ICS_BASE 0xc0005000 /* Interrupt controller */
#define SPI_FCTRL_BASE 0xc0006000 /* SPI flash controller registers */
#define DRAM_CTRL_BASE 0xc8000000 /* LiteDRAM control registers */
#define LETH_CSR_BASE 0xc8020000 /* LiteEth CSR registers */
#define LETH_SRAM_BASE 0xc8030000 /* LiteEth MMIO space */
#define SPI_FLASH_BASE 0xf0000000 /* SPI Flash memory map */
#define DRAM_INIT_BASE 0xff000000 /* Internal DRAM init firmware */
......@@ -22,6 +24,7 @@
* Interrupt numbers
*/
#define IRQ_UART0 0
#define IRQ_ETHERNET 1
/*
* Register definitions for the syscon registers
......@@ -33,6 +36,10 @@
#define SYS_REG_INFO_HAS_DRAM (1ull << 1)
#define SYS_REG_INFO_HAS_BRAM (1ull << 2)
#define SYS_REG_INFO_HAS_SPI_FLASH (1ull << 3)
#define SYS_REG_INFO_HAS_LITEETH (1ull << 4)
#define SYS_REG_INFO_HAS_LARGE_SYSCON (1ull << 5)
#define SYS_REG_INFO_HAS_UART1 (1ull << 6)
#define SYS_REG_INFO_HAS_ARTB (1ull << 7)
#define SYS_REG_BRAMINFO 0x10
#define SYS_REG_BRAMINFO_SIZE_MASK 0xfffffffffffffull
#define SYS_REG_DRAMINFO 0x18
......@@ -46,7 +53,9 @@
#define SYS_REG_DRAMINITINFO 0x30
#define SYS_REG_SPI_INFO 0x38
#define SYS_REG_SPI_INFO_FLASH_OFF_MASK 0xffffffff
#define SYS_REG_UART0_INFO 0x40
#define SYS_REG_UART1_INFO 0x48
#define SYS_REG_UART_IS_16550 (1ull << 32)
/*
......@@ -61,6 +70,59 @@
#define POTATO_CONSOLE_STATUS_TX_FULL 0x08
#define POTATO_CONSOLE_CLOCK_DIV 0x18
#define POTATO_CONSOLE_IRQ_EN 0x20
#define POTATO_CONSOLE_IRQ_RX 0x01
#define POTATO_CONSOLE_IRQ_TX 0x02
/*
* Register definitionss for our standard (16550 style) UART
*/
#define UART_REG_RX 0x00
#define UART_REG_TX 0x00
#define UART_REG_DLL 0x00
#define UART_REG_IER 0x04
#define UART_REG_IER_RDI 0x01
#define UART_REG_IER_THRI 0x02
#define UART_REG_IER_RLSI 0x04
#define UART_REG_IER_MSI 0x08
#define UART_REG_DLM 0x04
#define UART_REG_IIR 0x08
#define UART_REG_FCR 0x08
#define UART_REG_FCR_EN_FIFO 0x01
#define UART_REG_FCR_CLR_RCVR 0x02
#define UART_REG_FCR_CLR_XMIT 0x04
#define UART_REG_FCR_TRIG1 0x00
#define UART_REG_FCR_TRIG4 0x40
#define UART_REG_FCR_TRIG8 0x80
#define UART_REG_FCR_TRIG14 0xc0
#define UART_REG_LCR 0x0c
#define UART_REG_LCR_5BIT 0x00
#define UART_REG_LCR_6BIT 0x01
#define UART_REG_LCR_7BIT 0x02
#define UART_REG_LCR_8BIT 0x03
#define UART_REG_LCR_STOP 0x04
#define UART_REG_LCR_PAR 0x08
#define UART_REG_LCR_EVEN_PAR 0x10
#define UART_REG_LCR_STIC_PAR 0x20
#define UART_REG_LCR_BREAK 0x40
#define UART_REG_LCR_DLAB 0x80
#define UART_REG_MCR 0x10
#define UART_REG_MCR_DTR 0x01
#define UART_REG_MCR_RTS 0x02
#define UART_REG_MCR_OUT1 0x04
#define UART_REG_MCR_OUT2 0x08
#define UART_REG_MCR_LOOP 0x10
#define UART_REG_LSR 0x14
#define UART_REG_LSR_DR 0x01
#define UART_REG_LSR_OE 0x02
#define UART_REG_LSR_PE 0x04
#define UART_REG_LSR_FE 0x08
#define UART_REG_LSR_BI 0x10
#define UART_REG_LSR_THRE 0x20
#define UART_REG_LSR_TEMT 0x40
#define UART_REG_LSR_FIFOE 0x80
#define UART_REG_MSR 0x18
#define UART_REG_SCR 0x1c
/*
* Register definitions for the SPI controller
......
pythondata_cpu_microwatt/vhdl/lib/console.c
View file @ 5dc325fe
......@@ -5,22 +5,29 @@
#include "microwatt_soc.h"
#include "io.h"
#define UART_FREQ 115200
#define UART_BAUDS 115200
/*
* Core UART functions to implement for a port
*/
static uint64_t potato_uart_base;
bool uart_is_std;
static uint64_t uart_base;
static unsigned long uart_divisor(unsigned long uart_freq, unsigned long bauds)
{
return uart_freq / (bauds * 16);
}
static uint64_t potato_uart_reg_read(int offset)
{
return readq(potato_uart_base + offset);
return readq(uart_base + offset);
}
static void potato_uart_reg_write(int offset, uint64_t val)
{
writeq(val, potato_uart_base + offset);
writeq(val, uart_base + offset);
}
static int potato_uart_rx_empty(void)
......@@ -65,45 +72,93 @@ static void potato_uart_write(char c)
potato_uart_reg_write(POTATO_CONSOLE_TX, val);
}
static unsigned long potato_uart_divisor(unsigned long proc_freq, unsigned long uart_freq)
static void potato_uart_init(uint64_t uart_freq)
{
return proc_freq / (uart_freq * 16) - 1;
unsigned long div = uart_divisor(uart_freq, UART_BAUDS) - 1;
potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, div);
}
void potato_uart_init(void)
static void potato_uart_set_irq_en(bool rx_irq, bool tx_irq)
{
uint64_t proc_freq;
uint64_t en = 0;
potato_uart_base = UART_BASE;
proc_freq = readq(SYSCON_BASE + SYS_REG_CLKINFO) & SYS_REG_CLKINFO_FREQ_MASK;
if (rx_irq)
en |= POTATO_CONSOLE_IRQ_RX;
if (tx_irq)
en |= POTATO_CONSOLE_IRQ_TX;
potato_uart_reg_write(POTATO_CONSOLE_IRQ_EN, en);
}
potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, potato_uart_divisor(proc_freq, UART_FREQ));
static bool std_uart_rx_empty(void)
{
return !(readb(uart_base + UART_REG_LSR) & UART_REG_LSR_DR);
}
void potato_uart_irq_en(void)
static uint8_t std_uart_read(void)
{
potato_uart_reg_write(POTATO_CONSOLE_IRQ_EN, 0xff);
return readb(uart_base + UART_REG_RX);
}
void potato_uart_irq_dis(void)
static bool std_uart_tx_full(void)
{
potato_uart_reg_write(POTATO_CONSOLE_IRQ_EN, 0x00);
return !(readb(uart_base + UART_REG_LSR) & UART_REG_LSR_THRE);
}
int getchar(void)
static void std_uart_write(uint8_t c)
{
while (potato_uart_rx_empty())
/* Do nothing */ ;
writeb(c, uart_base + UART_REG_TX);
}
static void std_uart_set_irq_en(bool rx_irq, bool tx_irq)
{
uint8_t ier = 0;
return potato_uart_read();
if (tx_irq)
ier |= UART_REG_IER_THRI;
if (rx_irq)
ier |= UART_REG_IER_RDI;
writeb(ier, uart_base + UART_REG_IER);
}
int putchar(int c)
static void std_uart_init(uint64_t uart_freq)
{
unsigned long div = uart_divisor(uart_freq, UART_BAUDS);
writeb(UART_REG_LCR_DLAB, uart_base + UART_REG_LCR);
writeb(div & 0xff, uart_base + UART_REG_DLL);
writeb(div >> 8, uart_base + UART_REG_DLM);
writeb(UART_REG_LCR_8BIT, uart_base + UART_REG_LCR);
writeb(UART_REG_MCR_DTR |
UART_REG_MCR_RTS, uart_base + UART_REG_MCR);
writeb(UART_REG_FCR_EN_FIFO |
UART_REG_FCR_CLR_RCVR |
UART_REG_FCR_CLR_XMIT, uart_base + UART_REG_FCR);
}
int getchar(void)
{
while (potato_uart_tx_full())
/* Do Nothing */;
if (uart_is_std) {
while (std_uart_rx_empty())
/* Do nothing */ ;
return std_uart_read();
} else {
while (potato_uart_rx_empty())
/* Do nothing */ ;
return potato_uart_read();
}
}
potato_uart_write(c);
int putchar(int c)
{
if (uart_is_std) {
while(std_uart_tx_full())
/* Do Nothing */;
std_uart_write(c);
} else {
while (potato_uart_tx_full())
/* Do Nothing */;
potato_uart_write(c);
}
return c;
}
......@@ -131,3 +186,38 @@ size_t strlen(const char *s)
return len;
}
#endif
void console_init(void)
{
uint64_t sys_info;
uint64_t proc_freq;
uint64_t uart_info = 0;
uint64_t uart_freq = 0;
proc_freq = readq(SYSCON_BASE + SYS_REG_CLKINFO) & SYS_REG_CLKINFO_FREQ_MASK;
sys_info = readq(SYSCON_BASE + SYS_REG_INFO);
if (sys_info & SYS_REG_INFO_HAS_LARGE_SYSCON) {
uart_info = readq(SYSCON_BASE + SYS_REG_UART0_INFO);
uart_freq = uart_info & 0xffffffff;
}
if (uart_freq == 0)
uart_freq = proc_freq;
uart_base = UART_BASE;
if (uart_info & SYS_REG_UART_IS_16550) {
uart_is_std = true;
std_uart_init(proc_freq);
} else {
uart_is_std = false;
potato_uart_init(proc_freq);
}
}
void console_set_irq_en(bool rx_irq, bool tx_irq)
{
if (uart_is_std)
std_uart_set_irq_en(rx_irq, tx_irq);
else