Merge pull request #213 from ozbenh/uart16550

Add support for standard 16550 style UART

Makefile

@@ -55,8 +55,9 @@ soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_
 	spi_rxtx.vhdl spi_flash_ctrl.vhdl
 
 
-soc_sim_files = $(soc_files) sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl \
-	sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl
+soc_sim_files = $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
+	sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \
+	sim_16550_uart.vhdl
 
 soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
 	sim_jtag_socket_c.c

common.vhdl

@@ -27,6 +27,7 @@ package common is
     constant SPR_DSISR  : spr_num_t := 18;
     constant SPR_DAR    : spr_num_t := 19;
     constant SPR_TB     : spr_num_t := 268;
+    constant SPR_TBU    : spr_num_t := 269;
     constant SPR_DEC    : spr_num_t := 22;
     constant SPR_SRR0   : spr_num_t := 26;
     constant SPR_SRR1   : spr_num_t := 27;

execute1.vhdl

@@ -752,6 +752,9 @@ begin
 		    case decode_spr_num(e_in.insn) is
 		    when SPR_TB =>
 			spr_val := ctrl.tb;
+		    when SPR_TBU =>
+                        spr_val(63 downto 32) := (others => '0');
+			spr_val(31 downto 0)  := ctrl.tb(63 downto 32);
 		    when SPR_DEC =>
 			spr_val := ctrl.dec;
                     when 724 =>     -- LOG_ADDR SPR

fpga/arty_a7.xdc

@@ -13,10 +13,10 @@ set_property -dict { PACKAGE_PIN A9  IOSTANDARD LVCMOS33 } [get_ports { uart_mai
 # Pmod Header JC: UART (bottom)
 ################################################################################
 
-#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }];
-#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }];
-#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }];
-#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }];
+set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }];
+set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }];
+set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }];
+set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }];
 
 ################################################################################
 # RGB LEDs

fpga/top-arty.vhdl

@@ -22,7 +22,9 @@ entity toplevel is
         SPI_FLASH_DEF_CKDV : natural := 1;
         SPI_FLASH_DEF_QUAD : boolean := true;
         LOG_LENGTH         : natural := 512;
-        USE_LITEETH        : boolean  := false
+        USE_LITEETH        : boolean  := false;
+        UART_IS_16550      : boolean  := false;
+        HAS_UART1          : boolean  := true
         );
     port(
         ext_clk   : in  std_ulogic;
@@ -32,6 +34,12 @@ entity toplevel is
         uart_main_tx : out std_ulogic;
         uart_main_rx : in  std_ulogic;
 
+	-- UART1 signals:
+	uart_pmod_tx    : out std_ulogic;
+	uart_pmod_rx    : in std_ulogic;
+	uart_pmod_cts_n : in std_ulogic;
+	uart_pmod_rts_n : out std_ulogic;
+
         -- LEDs
         led0_b  : out std_ulogic;
         led0_g  : out std_ulogic;
@@ -170,7 +178,9 @@ begin
             SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
             SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
             LOG_LENGTH         => LOG_LENGTH,
-            USE_LITEETH        => USE_LITEETH
+            HAS_LITEETH        => USE_LITEETH,
+            UART0_IS_16550     => UART_IS_16550,
+            HAS_UART1          => HAS_UART1
             )
         port map (
             -- System signals
@@ -181,6 +191,10 @@ begin
             uart0_txd         => uart_main_tx,
             uart0_rxd         => uart_main_rx,
 
+	    -- UART1 signals
+	    uart1_txd         => uart_pmod_tx,
+	    uart1_rxd         => uart_pmod_rx,
+
             -- SPI signals
             spi_flash_sck     => spi_sck,
             spi_flash_cs_n    => spi_cs_n,
@@ -202,6 +216,8 @@ begin
             alt_reset            => core_alt_reset
             );
 
+    uart_pmod_rts_n <= '0';
+
     -- SPI Flash
     --
     -- Note: Unlike many other boards, the SPI flash on the Arty has

fpga/top-generic.vhdl

@@ -11,7 +11,8 @@ entity toplevel is
 	RESET_LOW     : boolean  := true;
 	CLK_INPUT     : positive := 100000000;
 	CLK_FREQUENCY : positive := 100000000;
-	DISABLE_FLATTEN_CORE : boolean := false
+	DISABLE_FLATTEN_CORE : boolean := false;
+        UART_IS_16550 : boolean  := true
 	);
     port(
 	ext_clk   : in  std_ulogic;
@@ -67,7 +68,8 @@ begin
 	    RAM_INIT_FILE => RAM_INIT_FILE,
 	    SIM           => false,
 	    CLK_FREQ      => CLK_FREQUENCY,
-	    DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE
+	    DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
+            UART0_IS_16550     => UART_IS_16550
 	    )
 	port map (
 	    system_clk        => system_clk,

fpga/top-nexys-video.vhdl

@@ -19,7 +19,8 @@ entity toplevel is
 	DISABLE_FLATTEN_CORE : boolean := false;
         SPI_FLASH_OFFSET   : integer := 10485760;
         SPI_FLASH_DEF_CKDV : natural := 1;
-        SPI_FLASH_DEF_QUAD : boolean := true
+        SPI_FLASH_DEF_QUAD : boolean := true;
+        UART_IS_16550      : boolean := true;
 	);
     port(
 	ext_clk   : in  std_ulogic;
@@ -126,7 +127,8 @@ begin
             SPI_FLASH_DLINES   => 4,
             SPI_FLASH_OFFSET   => SPI_FLASH_OFFSET,
             SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
-            SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD
+            SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
+            UART0_IS_16550     => UART_IS_16550
 	    )
 	port map (
             -- System signals

hello_world/hello_world.c

@@ -7,7 +7,7 @@
 
 int main(void)
 {
-	potato_uart_init();
+	console_init();
 
 	puts(HELLO_WORLD);
 

hello_world/hello_world.hex

@@ -514,73 +514,118 @@ e8010010ebc1fff0
 7c0803a6ebe1fff8
 3c4000014e800020
 7c0802a63842a000
-3fe2fffffbe1fff8
-f80100103bff7240
-48000051f821ffd1
-7fe3fb7860000000
-60000000480001d5
-7fe3fb787c641b78
-600000004800017d
-60000000480000ed
-480001295463063e
+f821ffe1f8010010
+60000000480001dd
+386373a83c62ffff
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+600000004800002d
+480000a95463063e
 4bffffec60000000
 0100000000000000
-3c40000100000180
-3d20c0003842a000
-6129200060000000
-f922800079290020
-612900203d20c000
-7c0004ac79290020
-3d40001c7d204eea
-7d295392614a2000
-394a0018e9428000
-7c0004ac3929ffff
-4e8000207d2057ea
-0000000000000000
-3c40000100000000
+3c40000100000080
 600000003842a000
-394000ffe9228000
-7c0004ac39290020
-4e8000207d404fea
+6000000039228000
+8929000039428008
+419e00302f890000
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+7c0004ac39290010
+712900017d204eea
+e86a00004082ffec
+7c0004ac38630008
+4bffffd07c601eea
 0000000000000000
 3c40000100000000
 600000003842a000
-39400000e9228000
-7c0004ac39290020
-4e8000207d404fea
+6000000039228000
+8929000039428008
+419e002c2f890000
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+7c0004ace92a0000
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+4082ffec71290008
+e94a00005469063e
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+000000004e800020
+0000000000000000
+3842a0003c400001
+fbc1fff07c0802a6
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+000000004bffffd0
+0000028001000000
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+4bffffe839290001
 0000000000000000
 3c40000100000000
-600000003842a000
-39290010e9228000
+3d20c0003842a000
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 7d204eea7c0004ac
-4082ffe871290001
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+7c0004ac39290008
+4e8000207d404faa
+990700003d40c000
+614a20183929ffff
+7c0004ac794a0020
+4e8000207d2057ea
 0000000000000000
 3c40000100000000
 600000003842a000
-39290010e9228000
-7d204eea7c0004ac
-4082ffe871290008
-7c0004ace9228000
+2ea4000039228000
+2f89000089290000
+e922800860000000
+41960024419e0030
+2fa3000039400002
+614a0001419e0008
+7c0004ac39290004
+4e8000207d404faa
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+7c0004ac39290020
 4e8000207c604fea
 0000000000000000
-3c40000100000000
-7c0802a63842a000
-fbe1fff8fbc1fff0
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-f821ffd1f8010010
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-0100000000000000
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-2f8a00007d4348ae
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-392900014e800020
-000000004bffffe8
 0000000000000000
 6f57206f6c6c6548
-0000000a0d646c72
+000000000a646c72

include/console.h

 #include <stddef.h>
 
-void potato_uart_init(void);
-void potato_uart_irq_en(void);
-void potato_uart_irq_dis(void);
+void console_init(void);
+void console_set_irq_en(bool rx_irq, bool tx_irq);
 int getchar(void);
 int putchar(int c);
 int puts(const char *str);

include/microwatt_soc.h

@@ -37,6 +37,9 @@
 #define   SYS_REG_INFO_HAS_BRAM 		(1ull << 2)
 #define   SYS_REG_INFO_HAS_SPI_FLASH 		(1ull << 3)
 #define   SYS_REG_INFO_HAS_LITEETH 		(1ull << 4)
+#define   SYS_REG_INFO_HAS_LARGE_SYSCON	        (1ull << 5)
+#define   SYS_REG_INFO_HAS_UART1 		(1ull << 6)
+#define   SYS_REG_INFO_HAS_ARTB                 (1ull << 7)
 #define SYS_REG_BRAMINFO		0x10
 #define   SYS_REG_BRAMINFO_SIZE_MASK		0xfffffffffffffull
 #define SYS_REG_DRAMINFO		0x18
@@ -50,7 +53,9 @@
 #define SYS_REG_DRAMINITINFO		0x30
 #define SYS_REG_SPI_INFO		0x38
 #define   SYS_REG_SPI_INFO_FLASH_OFF_MASK	0xffffffff
-
+#define SYS_REG_UART0_INFO		0x40
+#define SYS_REG_UART1_INFO		0x48
+#define   SYS_REG_UART_IS_16550			(1ull << 32)
 
 
 /*
@@ -65,6 +70,59 @@
 #define   POTATO_CONSOLE_STATUS_TX_FULL			0x08
 #define POTATO_CONSOLE_CLOCK_DIV	0x18
 #define POTATO_CONSOLE_IRQ_EN		0x20
+#define   POTATO_CONSOLE_IRQ_RX				0x01
+#define   POTATO_CONSOLE_IRQ_TX				0x02
+
+/*
+ * Register definitionss for our standard (16550 style) UART
+ */
+#define UART_REG_RX       0x00
+#define UART_REG_TX       0x00
+#define UART_REG_DLL      0x00
+#define UART_REG_IER      0x04
+#define   UART_REG_IER_RDI      0x01
+#define   UART_REG_IER_THRI     0x02
+#define   UART_REG_IER_RLSI     0x04
+#define   UART_REG_IER_MSI      0x08
+#define UART_REG_DLM      0x04
+#define UART_REG_IIR      0x08
+#define UART_REG_FCR      0x08
+#define   UART_REG_FCR_EN_FIFO  0x01
+#define   UART_REG_FCR_CLR_RCVR 0x02
+#define   UART_REG_FCR_CLR_XMIT 0x04
+#define   UART_REG_FCR_TRIG1    0x00
+#define   UART_REG_FCR_TRIG4    0x40
+#define   UART_REG_FCR_TRIG8    0x80
+#define   UART_REG_FCR_TRIG14   0xc0
+#define UART_REG_LCR      0x0c
+#define   UART_REG_LCR_5BIT	0x00
+#define   UART_REG_LCR_6BIT	0x01
+#define   UART_REG_LCR_7BIT	0x02
+#define   UART_REG_LCR_8BIT	0x03
+#define   UART_REG_LCR_STOP     0x04
+#define   UART_REG_LCR_PAR      0x08
+#define   UART_REG_LCR_EVEN_PAR 0x10
+#define   UART_REG_LCR_STIC_PAR 0x20
+#define   UART_REG_LCR_BREAK    0x40
+#define   UART_REG_LCR_DLAB     0x80
+#define UART_REG_MCR      0x10
+#define   UART_REG_MCR_DTR      0x01
+#define   UART_REG_MCR_RTS      0x02
+#define   UART_REG_MCR_OUT1     0x04
+#define   UART_REG_MCR_OUT2     0x08
+#define   UART_REG_MCR_LOOP     0x10
+#define UART_REG_LSR      0x14
+#define   UART_REG_LSR_DR       0x01
+#define   UART_REG_LSR_OE       0x02
+#define   UART_REG_LSR_PE       0x04
+#define   UART_REG_LSR_FE       0x08
+#define   UART_REG_LSR_BI       0x10
+#define   UART_REG_LSR_THRE     0x20
+#define   UART_REG_LSR_TEMT     0x40
+#define   UART_REG_LSR_FIFOE    0x80
+#define UART_REG_MSR      0x18
+#define UART_REG_SCR      0x1c
+
 
 /*
  * Register definitions for the SPI controller

lib/console.c

@@ -5,22 +5,29 @@
 #include "microwatt_soc.h"
 #include "io.h"
 
-#define UART_FREQ 115200
+#define UART_BAUDS 115200
 
 /*
  * Core UART functions to implement for a port
  */
 
-static uint64_t potato_uart_base;
+bool uart_is_std;
+
+static uint64_t uart_base;
+
+static unsigned long uart_divisor(unsigned long uart_freq, unsigned long bauds)
+{
+	return uart_freq / (bauds * 16);
+}
 
 static uint64_t potato_uart_reg_read(int offset)
 {
-	return readq(potato_uart_base + offset);
+	return readq(uart_base + offset);
 }
 
 static void potato_uart_reg_write(int offset, uint64_t val)
 {
-	writeq(val, potato_uart_base + offset);
+	writeq(val, uart_base + offset);
 }
 
 static int potato_uart_rx_empty(void)
@@ -65,45 +72,93 @@ static void potato_uart_write(char c)
 	potato_uart_reg_write(POTATO_CONSOLE_TX, val);
 }
 
-static unsigned long potato_uart_divisor(unsigned long proc_freq, unsigned long uart_freq)
+static void potato_uart_init(uint64_t uart_freq)
 {
-	return proc_freq / (uart_freq * 16) - 1;
+	unsigned long div = uart_divisor(uart_freq, UART_BAUDS) - 1;
+	potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, div);
 }
 
-void potato_uart_init(void)
+static void potato_uart_set_irq_en(bool rx_irq, bool tx_irq)
 {
-	uint64_t proc_freq;
+	uint64_t en = 0;
 
-	potato_uart_base = UART_BASE;
-	proc_freq = readq(SYSCON_BASE + SYS_REG_CLKINFO) & SYS_REG_CLKINFO_FREQ_MASK;
+	if (rx_irq)
+		en |= POTATO_CONSOLE_IRQ_RX;
+	if (tx_irq)
+		en |= POTATO_CONSOLE_IRQ_TX;
+	potato_uart_reg_write(POTATO_CONSOLE_IRQ_EN, en);
+}
 
-	potato_uart_reg_write(POTATO_CONSOLE_CLOCK_DIV, potato_uart_divisor(proc_freq, UART_FREQ));
+static bool std_uart_rx_empty(void)
+{
+	return !(readb(uart_base + UART_REG_LSR) & UART_REG_LSR_DR);
 }
 
-void potato_uart_irq_en(void)
+static uint8_t std_uart_read(void)
 {
-	potato_uart_reg_write(POTATO_CONSOLE_IRQ_EN, 0xff);
+	return readb(uart_base + UART_REG_RX);
 }
 
-void potato_uart_irq_dis(void)
+static bool std_uart_tx_full(void)
 {
-	potato_uart_reg_write(POTATO_CONSOLE_IRQ_EN, 0x00);
+	return !(readb(uart_base + UART_REG_LSR) & UART_REG_LSR_THRE);
 }
 
-int getchar(void)
+static void std_uart_write(uint8_t c)
 {
-	while (potato_uart_rx_empty())
-		/* Do nothing */ ;
+	writeb(c, uart_base + UART_REG_TX);
+}
+
+static void std_uart_set_irq_en(bool rx_irq, bool tx_irq)
+{
+	uint8_t ier = 0;
 
-	return potato_uart_read();
+	if (tx_irq)
+		ier |= UART_REG_IER_THRI;
+	if (rx_irq)
+		ier |= UART_REG_IER_RDI;
+	writeb(ier, uart_base + UART_REG_IER);
 }
 
-int putchar(int c)
+static void std_uart_init(uint64_t uart_freq)
+{
+	unsigned long div = uart_divisor(uart_freq, UART_BAUDS);
+	
+	writeb(UART_REG_LCR_DLAB,     uart_base + UART_REG_LCR);
+	writeb(div & 0xff,            uart_base + UART_REG_DLL);
+	writeb(div >> 8,              uart_base + UART_REG_DLM);
+	writeb(UART_REG_LCR_8BIT,     uart_base + UART_REG_LCR);
+	writeb(UART_REG_MCR_DTR |
+	       UART_REG_MCR_RTS,      uart_base + UART_REG_MCR);
+	writeb(UART_REG_FCR_EN_FIFO |
+	       UART_REG_FCR_CLR_RCVR |
+	       UART_REG_FCR_CLR_XMIT, uart_base + UART_REG_FCR);
+}
+
+int getchar(void)
 {
-	while (potato_uart_tx_full())
-		/* Do Nothing */;
+	if (uart_is_std) {
+		while (std_uart_rx_empty())
+			/* Do nothing */ ;
+		return std_uart_read();
+	} else {
+		while (potato_uart_rx_empty())
+			/* Do nothing */ ;
+		return potato_uart_read();
+	}
+}
 
-	potato_uart_write(c);
+int putchar(int c)
+{
+	if (uart_is_std) {
+		while(std_uart_tx_full())
+			/* Do Nothing */;
+		std_uart_write(c);
+	} else {
+		while (potato_uart_tx_full())
+			/* Do Nothing */;
+		potato_uart_write(c);
+	}
 	return c;
 }
 
@@ -131,3 +186,38 @@ size_t strlen(const char *s)
 	return len;
 }
 #endif
+
+void console_init(void)
+{
+	uint64_t sys_info;
+	uint64_t proc_freq;
+	uint64_t uart_info = 0;
+	uint64_t uart_freq = 0;
+
+	proc_freq = readq(SYSCON_BASE + SYS_REG_CLKINFO) & SYS_REG_CLKINFO_FREQ_MASK;
+	sys_info  = readq(SYSCON_BASE + SYS_REG_INFO);
+
+	if (sys_info & SYS_REG_INFO_HAS_LARGE_SYSCON) {
+		uart_info = readq(SYSCON_BASE + SYS_REG_UART0_INFO);
+		uart_freq = uart_info & 0xffffffff;
+	}
+	if (uart_freq == 0)
+		uart_freq = proc_freq;
+
+	uart_base = UART_BASE;
+	if (uart_info & SYS_REG_UART_IS_16550) {
+		uart_is_std = true;
+		std_uart_init(proc_freq);
+	} else {
+		uart_is_std = false;
+		potato_uart_init(proc_freq);
+	}
+}
+
+void console_set_irq_en(bool rx_irq, bool tx_irq)
+{
+	if (uart_is_std)
+		std_uart_set_irq_en(rx_irq, tx_irq);
+	else
+		potato_uart_set_irq_en(rx_irq, tx_irq);
+}

litedram/gen-src/sdram_init/main.c

@@ -241,7 +241,7 @@ uint64_t main(void)
 	bool try_flash = false;
 
 	/* Init the UART */
-	potato_uart_init();
+	console_init();
 
 	printf("\n\nWelcome to Microwatt !\n\n");
 

microwatt.core

@@ -103,10 +103,13 @@ filesets:
   liteeth:
       depend : [":microwatt:liteeth"]
 
+  uart16550:
+      depend : ["::uart16550"]
+
 targets:
   nexys_a7:
     default_tool: vivado
-    filesets: [core, nexys_a7, soc, fpga, debug_xilinx, xilinx_specific]
+    filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
     parameters :
       - memory_size
       - ram_init_file
@@ -114,13 +117,15 @@ targets:
       - clk_frequency
       - disable_flatten_core
       - log_length=2048
+      - uart_is_16550
+      - has_uart1
     tools:
       vivado: {part : xc7a100tcsg324-1}
     toplevel : toplevel
 
   nexys_video-nodram:
     default_tool: vivado
-    filesets: [core, nexys_video, soc, fpga, debug_xilinx, xilinx_specific]
+    filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
     parameters :
       - memory_size
       - ram_init_file
@@ -129,13 +134,15 @@ targets:
       - disable_flatten_core
       - spi_flash_offset=10485760
       - log_length=2048
+      - uart_is_16550
+      - has_uart1
     tools:
       vivado: {part : xc7a200tsbg484-1}
     toplevel : toplevel
 
   nexys_video:
     default_tool: vivado
-    filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, xilinx_specific]
+    filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
     parameters:
       - memory_size
       - ram_init_file
@@ -151,7 +158,7 @@ targets:
 
   arty_a7-35-nodram:
     default_tool: vivado
-    filesets: [core, arty_a7, soc, fpga, debug_xilinx, xilinx_specific]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
     parameters :
       - memory_size
       - ram_init_file
@@ -160,13 +167,15 @@ targets:
       - disable_flatten_core
       - spi_flash_offset=3145728
       - log_length=512
+      - uart_is_16550
+      - has_uart1
     tools:
       vivado: {part : xc7a35ticsg324-1L}
     toplevel : toplevel
 
   arty_a7-35:
     default_tool: vivado
-    filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, xilinx_specific]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
     parameters :
       - memory_size
       - ram_init_file
@@ -176,6 +185,8 @@ targets:
       - no_bram
       - spi_flash_offset=3145728
       - log_length=512
+      - uart_is_16550
+      - has_uart1
     generate: [litedram_arty, liteeth_arty]
     tools:
       vivado: {part : xc7a35ticsg324-1L}
@@ -183,7 +194,7 @@ targets:
 
   arty_a7-100-nodram:
     default_tool: vivado
-    filesets: [core, arty_a7, soc, fpga, debug_xilinx, xilinx_specific]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
     parameters :
       - memory_size
       - ram_init_file
@@ -192,13 +203,15 @@ targets:
       - disable_flatten_core
       - spi_flash_offset=4194304
       - log_length=2048
+      - uart_is_16550
+      - has_uart1
     tools:
       vivado: {part : xc7a100ticsg324-1L}
     toplevel : toplevel
 
   arty_a7-100:
     default_tool: vivado
-    filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, xilinx_specific]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
     parameters:
       - memory_size
       - ram_init_file
@@ -208,6 +221,8 @@ targets:
       - no_bram
       - spi_flash_offset=4194304
       - log_length=2048
+      - uart_is_16550
+      - has_uart1
     generate: [litedram_arty, liteeth_arty]
     tools:
       vivado: {part : xc7a100ticsg324-1L}
@@ -215,7 +230,7 @@ targets: