Add optional PC/LR debug signals to Microwatt

pythondata_cpu_microwatt/vhdl/core.vhdl

@@ -35,6 +35,10 @@ entity core is
 	dmi_wr		: in std_ulogic;
 	dmi_ack	        : out std_ulogic;
 
+        -- Optional debug signals for OS bringup
+	current_pc      : out std_ulogic_vector(63 downto 0);
+	current_lr      : out std_ulogic_vector(63 downto 0);
+
 	ext_irq		: in std_ulogic;
 
 	terminated_out   : out std_logic
@@ -42,6 +46,9 @@ entity core is
 end core;
 
 architecture behave of core is
+    -- optional LR debug signal
+    signal debug_lr : std_ulogic_vector(63 downto 0);
+
     -- icache signals
     signal fetch1_to_icache : Fetch1ToIcacheType;
     signal icache_to_decode1 : IcacheToDecode1Type;
@@ -160,6 +167,10 @@ begin
 
     core_rst <= dbg_core_rst or rst;
 
+    -- optional debug signals for OS bringup
+    current_pc <= fetch1_to_icache.nia;
+    current_lr <= debug_lr;
+
     resets: process(clk)
     begin
         if rising_edge(clk) then
@@ -308,6 +319,7 @@ begin
 	    icache_inval => ex1_icache_inval,
             dbg_msr_out => msr,
             terminate_out => terminate,
+            debug_lr =>  debug_lr,
             log_out => log_data(134 downto 120),
             log_rd_addr => log_rd_addr,
             log_rd_data => log_rd_data,

pythondata_cpu_microwatt/vhdl/execute1.vhdl

@@ -38,6 +38,8 @@ entity execute1 is
 	icache_inval : out std_ulogic;
 	terminate_out : out std_ulogic;
 
+        debug_lr : out std_ulogic_vector(63 downto 0);
+
         log_out : out std_ulogic_vector(14 downto 0);
         log_rd_addr : out std_ulogic_vector(31 downto 0);
         log_rd_data : in std_ulogic_vector(63 downto 0);
@@ -51,6 +53,7 @@ architecture behaviour of execute1 is
         f : Execute1ToFetch1Type;
         busy: std_ulogic;
         terminate: std_ulogic;
+        debug_lr_reg : std_ulogic_vector(63 downto 0);
 	lr_update : std_ulogic;
 	next_lr : std_ulogic_vector(63 downto 0);
 	mul_in_progress : std_ulogic;
@@ -66,7 +69,7 @@ architecture behaviour of execute1 is
     end record;
     constant reg_type_init : reg_type :=
         (e => Execute1ToWritebackInit, f => Execute1ToFetch1Init,
-         busy => '0', lr_update => '0', terminate => '0',
+         busy => '0', debug_lr_reg => (others => '0'), lr_update => '0', terminate => '0',
          mul_in_progress => '0', div_in_progress => '0', cntz_in_progress => '0',
          slow_op_insn => OP_ILLEGAL, slow_op_rc => '0', slow_op_oe => '0', slow_op_xerc => xerc_init,
          next_lr => (others => '0'), last_nia => (others => '0'), others => (others => '0'));
@@ -99,6 +102,9 @@ architecture behaviour of execute1 is
     signal irq_valid_log : std_ulogic;
     signal log_data : std_ulogic_vector(14 downto 0);
 
+    -- optional LR debug signal
+    signal debug_lr_wire : std_ulogic_vector(63 downto 0);
+
     type privilege_level is (USER, SUPER);
     type op_privilege_array is array(insn_type_t) of privilege_level;
     constant op_privilege: op_privilege_array := (
@@ -248,6 +254,8 @@ begin
 
     terminate_out <= r.terminate;
 
+    debug_lr <= debug_lr_wire;
+
     execute1_0: process(clk)
     begin
 	if rising_edge(clk) then
@@ -265,6 +273,7 @@ begin
                     report "LR update to " & to_hstring(r.next_lr);
                 end if;
             end if;
+
 	end if;
     end process;
 
@@ -924,6 +933,7 @@ begin
             -- exc_write path since next_nia is written through that path
             -- in other places.
 	    if e_in.lr = '1' then
+                v.debug_lr_reg := next_nia;
                 if result_en = '0' then
                     v.e.exc_write_enable := '1';
                     v.e.exc_write_data := next_nia;
@@ -946,6 +956,7 @@ begin
         elsif r.f.redirect = '1' then
             v.e.valid := '1';
 	elsif r.lr_update = '1' then
+            v.debug_lr_reg := r.next_lr;
             v.e.exc_write_enable := '1';
 	    v.e.exc_write_data := r.next_lr;
 	    v.e.exc_write_reg := fast_spr_num(SPR_LR);
@@ -1090,6 +1101,8 @@ begin
 
         exception_log <= exception;
         irq_valid_log <= irq_valid;
+
+        debug_lr_wire <= v.debug_lr_reg;
     end process;
 
     ex1_log : process(clk)