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Kestrel Collaboration
Kestrel LiteX
migen
Commits
fa63cc1e
Commit
fa63cc1e
authored
12 years ago
by
Sebastien Bourdeauducq
Browse files
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fhdl: replication support
parent
5c7131dc
Changes
3
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Showing
3 changed files
with
21 additions
and
4 deletions
+21
-4
migen/fhdl/convtools.py
migen/fhdl/convtools.py
+4
-0
migen/fhdl/structure.py
migen/fhdl/structure.py
+15
-4
migen/fhdl/verilog.py
migen/fhdl/verilog.py
+2
-0
No files found.
migen/fhdl/convtools.py
View file @
fa63cc1e
...
@@ -37,6 +37,8 @@ def ListSignals(node):
...
@@ -37,6 +37,8 @@ def ListSignals(node):
elif
isinstance
(
node
,
Cat
):
elif
isinstance
(
node
,
Cat
):
l
=
list
(
map
(
ListSignals
,
node
.
l
))
l
=
list
(
map
(
ListSignals
,
node
.
l
))
return
set
().
union
(
*
l
)
return
set
().
union
(
*
l
)
elif
isinstance
(
node
,
Replicate
):
return
ListSignals
(
node
.
v
)
elif
isinstance
(
node
,
Assign
):
elif
isinstance
(
node
,
Assign
):
return
ListSignals
(
node
.
l
)
|
ListSignals
(
node
.
r
)
return
ListSignals
(
node
.
l
)
|
ListSignals
(
node
.
r
)
elif
isinstance
(
node
,
StatementList
):
elif
isinstance
(
node
,
StatementList
):
...
@@ -60,6 +62,8 @@ def ListTargets(node):
...
@@ -60,6 +62,8 @@ def ListTargets(node):
elif
isinstance
(
node
,
Cat
):
elif
isinstance
(
node
,
Cat
):
l
=
list
(
map
(
ListTargets
,
node
.
l
))
l
=
list
(
map
(
ListTargets
,
node
.
l
))
return
set
().
union
(
*
l
)
return
set
().
union
(
*
l
)
elif
isinstance
(
node
,
Replicate
):
return
ListTargets
(
node
.
v
)
elif
isinstance
(
node
,
Assign
):
elif
isinstance
(
node
,
Assign
):
return
ListTargets
(
node
.
l
)
return
ListTargets
(
node
.
l
)
elif
isinstance
(
node
,
StatementList
):
elif
isinstance
(
node
,
StatementList
):
...
...
This diff is collapsed.
Click to expand it.
migen/fhdl/structure.py
View file @
fa63cc1e
import
math
import
math
def
BitsFor
(
n
):
def
BitsFor
(
n
):
if
n
==
0
:
if
isinstance
(
n
,
Constant
)
:
return
1
return
n
.
bv
.
width
else
:
else
:
return
int
(
math
.
ceil
(
math
.
log
(
n
+
1
,
2
)))
if
n
==
0
:
return
1
else
:
return
int
(
math
.
ceil
(
math
.
log
(
n
+
1
,
2
)))
class
BV
:
class
BV
:
def
__init__
(
self
,
width
=
1
,
signed
=
False
):
def
__init__
(
self
,
width
=
1
,
signed
=
False
):
self
.
width
=
width
self
.
width
=
width
self
.
signed
=
signed
self
.
signed
=
signed
def
__
st
r__
(
self
):
def
__
rep
r__
(
self
):
r
=
str
(
self
.
width
)
+
"'"
r
=
str
(
self
.
width
)
+
"'"
if
self
.
signed
:
if
self
.
signed
:
r
+=
"s"
r
+=
"s"
...
@@ -98,10 +101,18 @@ class Cat(Value):
...
@@ -98,10 +101,18 @@ class Cat(Value):
def
__init__
(
self
,
*
args
):
def
__init__
(
self
,
*
args
):
self
.
l
=
list
(
map
(
_cst
,
args
))
self
.
l
=
list
(
map
(
_cst
,
args
))
class
Replicate
(
Value
):
def
__init__
(
self
,
v
,
n
):
self
.
v
=
v
self
.
n
=
n
class
Constant
(
Value
):
class
Constant
(
Value
):
def
__init__
(
self
,
n
,
bv
=
None
):
def
__init__
(
self
,
n
,
bv
=
None
):
self
.
bv
=
bv
or
BV
(
BitsFor
(
n
))
self
.
bv
=
bv
or
BV
(
BitsFor
(
n
))
self
.
n
=
n
self
.
n
=
n
def
__repr__
(
self
):
return
str
(
self
.
bv
)
+
str
(
self
.
n
)
def
_cst
(
x
):
def
_cst
(
x
):
if
isinstance
(
x
,
int
):
if
isinstance
(
x
,
int
):
...
...
This diff is collapsed.
Click to expand it.
migen/fhdl/verilog.py
View file @
fa63cc1e
...
@@ -39,6 +39,8 @@ def _printexpr(ns, node):
...
@@ -39,6 +39,8 @@ def _printexpr(ns, node):
l
=
list
(
map
(
partial
(
_printexpr
,
ns
),
node
.
l
))
l
=
list
(
map
(
partial
(
_printexpr
,
ns
),
node
.
l
))
l
.
reverse
()
l
.
reverse
()
return
"{"
+
", "
.
join
(
l
)
+
"}"
return
"{"
+
", "
.
join
(
l
)
+
"}"
elif
isinstance
(
node
,
Replicate
):
return
"{"
+
str
(
node
.
n
)
+
"{"
+
_printexpr
(
ns
,
node
.
v
)
+
"}}"
else
:
else
:
raise
TypeError
raise
TypeError
...
...
This diff is collapsed.
Click to expand it.
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