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Kestrel Collaboration
Kestrel LiteX
migen
Commits
d1c52523
Commit
d1c52523
authored
8 years ago
by
Sebastien Bourdeauducq
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kc705: automatic Ethernet TX clock constraint
parent
a3616119
Changes
1
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migen/build/platforms/kc705.py
migen/build/platforms/kc705.py
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migen/build/platforms/kc705.py
View file @
d1c52523
...
@@ -502,6 +502,10 @@ class Platform(XilinxPlatform):
...
@@ -502,6 +502,10 @@ class Platform(XilinxPlatform):
self
.
add_period_constraint
(
self
.
lookup_request
(
"eth_clocks"
).
rx
,
8.0
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"eth_clocks"
).
rx
,
8.0
)
except
ConstraintError
:
except
ConstraintError
:
pass
pass
try
:
self
.
add_period_constraint
(
self
.
lookup_request
(
"eth_clocks"
).
tx
,
8.0
)
except
ConstraintError
:
pass
if
isinstance
(
self
.
toolchain
,
XilinxISEToolchain
):
if
isinstance
(
self
.
toolchain
,
XilinxISEToolchain
):
self
.
add_platform_command
(
"CONFIG DCI_CASCADE =
\"
33 32 34
\"
;"
)
self
.
add_platform_command
(
"CONFIG DCI_CASCADE =
\"
33 32 34
\"
;"
)
else
:
else
:
...
...
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