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Kestrel Collaboration
Kestrel LiteX
migen
Commits
cb5e0953
Commit
cb5e0953
authored
11 years ago
by
Robert Jördens
Committed by
Sebastien Bourdeauducq
11 years ago
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migen/test: start unittests
parent
55afab22
Changes
3
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25 additions
and
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+25
-0
migen/test/__init__.py
migen/test/__init__.py
+0
-0
migen/test/support.py
migen/test/support.py
+24
-0
setup.py
setup.py
+1
-0
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migen/test/__init__.py
0 → 100644
View file @
cb5e0953
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migen/test/support.py
0 → 100644
View file @
cb5e0953
import
unittest
from
migen.fhdl.std
import
*
from
migen.sim.generic
import
Simulator
from
migen.fhdl
import
verilog
class
SimBench
(
Module
):
callback
=
None
def
do_simulation
(
self
,
s
):
if
self
.
callback
is
not
None
:
return
self
.
callback
(
self
,
s
)
class
SimCase
(
unittest
.
TestCase
):
TestBench
=
SimBench
def
setUp
(
self
):
self
.
tb
=
self
.
TestBench
()
def
test_to_verilog
(
self
):
verilog
.
convert
(
self
.
tb
)
def
run_with
(
self
,
cb
,
cycles
=-
1
):
self
.
tb
.
callback
=
cb
with
Simulator
(
self
.
tb
)
as
s
:
s
.
run
(
cycles
)
This diff is collapsed.
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setup.py
View file @
cb5e0953
...
@@ -22,6 +22,7 @@ setup(
...
@@ -22,6 +22,7 @@ setup(
url
=
"http://www.milkymist.org"
,
url
=
"http://www.milkymist.org"
,
download_url
=
"https://github.com/milkymist/migen"
,
download_url
=
"https://github.com/milkymist/migen"
,
packages
=
find_packages
(
here
),
packages
=
find_packages
(
here
),
test_suite
=
"migen.test"
,
license
=
"BSD"
,
license
=
"BSD"
,
platforms
=
[
"Any"
],
platforms
=
[
"Any"
],
keywords
=
"HDL ASIC FPGA hardware design"
,
keywords
=
"HDL ASIC FPGA hardware design"
,
...
...
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