Commit cb5e0953 authored by Robert Jördens's avatar Robert Jördens Committed by Sebastien Bourdeauducq
Browse files

migen/test: start unittests

parent 55afab22
import unittest
from migen.fhdl.std import *
from migen.sim.generic import Simulator
from migen.fhdl import verilog
class SimBench(Module):
callback = None
def do_simulation(self, s):
if self.callback is not None:
return self.callback(self, s)
class SimCase(unittest.TestCase):
TestBench = SimBench
def setUp(self):
self.tb = self.TestBench()
def test_to_verilog(self):
verilog.convert(self.tb)
def run_with(self, cb, cycles=-1):
self.tb.callback = cb
with Simulator(self.tb) as s:
s.run(cycles)
...@@ -22,6 +22,7 @@ setup( ...@@ -22,6 +22,7 @@ setup(
url="http://www.milkymist.org", url="http://www.milkymist.org",
download_url="https://github.com/milkymist/migen", download_url="https://github.com/milkymist/migen",
packages=find_packages(here), packages=find_packages(here),
test_suite="migen.test",
license="BSD", license="BSD",
platforms=["Any"], platforms=["Any"],
keywords="HDL ASIC FPGA hardware design", keywords="HDL ASIC FPGA hardware design",
......
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