Commit a81781f5 authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
Browse files

fhdl/specials: allow setting memory name

parent 425de02f
...@@ -180,12 +180,13 @@ class _MemoryPort: ...@@ -180,12 +180,13 @@ class _MemoryPort:
self.clock_domain = clock_domain self.clock_domain = clock_domain
class Memory(Special): class Memory(Special):
def __init__(self, width, depth, init=None): def __init__(self, width, depth, init=None, name="mem"):
Special.__init__(self) Special.__init__(self)
self.width = width self.width = width
self.depth = depth self.depth = depth
self.ports = [] self.ports = []
self.init = init self.init = init
self.name_override = name
def get_port(self, write_capable=False, async_read=False, def get_port(self, write_capable=False, async_read=False,
has_re=False, we_granularity=0, mode=WRITE_FIRST, has_re=False, we_granularity=0, mode=WRITE_FIRST,
...@@ -234,8 +235,6 @@ class Memory(Special): ...@@ -234,8 +235,6 @@ class Memory(Special):
add(p.dat_r) add(p.dat_r)
return s return s
name_override = "mem"
@staticmethod @staticmethod
def emit_verilog(memory, ns, clock_domains): def emit_verilog(memory, ns, clock_domains):
r = "" r = ""
......
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