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Kestrel Collaboration
Kestrel LiteX
migen
Commits
a3cc6120
Commit
a3cc6120
authored
8 years ago
by
whitequark
Browse files
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fhdl.verilog: escape names not starting with [a-zA-Z_].
parent
2b76c23e
Changes
1
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Showing
1 changed file
with
18 additions
and
7 deletions
+18
-7
migen/fhdl/verilog.py
migen/fhdl/verilog.py
+18
-7
No files found.
migen/fhdl/verilog.py
View file @
a3cc6120
from
functools
import
partial
from
functools
import
partial
from
operator
import
itemgetter
from
operator
import
itemgetter
import
collections
import
collections
import
re
from
migen.fhdl.structure
import
*
from
migen.fhdl.structure
import
*
from
migen.fhdl.structure
import
_Operator
,
_Slice
,
_Assign
,
_Fragment
from
migen.fhdl.structure
import
_Operator
,
_Slice
,
_Assign
,
_Fragment
...
@@ -31,6 +32,16 @@ _reserved_keywords = {
...
@@ -31,6 +32,16 @@ _reserved_keywords = {
}
}
_name_re
=
re
.
compile
(
"^[a-zA-Z_]"
)
def
_printname
(
ns
,
s
):
n
=
ns
.
get_name
(
s
)
if
_name_re
.
match
(
n
):
return
n
else
:
return
"
\\
"
+
n
+
" "
def
_printsig
(
ns
,
s
):
def
_printsig
(
ns
,
s
):
if
s
.
signed
:
if
s
.
signed
:
n
=
"signed "
n
=
"signed "
...
@@ -38,7 +49,7 @@ def _printsig(ns, s):
...
@@ -38,7 +49,7 @@ def _printsig(ns, s):
n
=
""
n
=
""
if
len
(
s
)
>
1
:
if
len
(
s
)
>
1
:
n
+=
"["
+
str
(
len
(
s
)
-
1
)
+
":0] "
n
+=
"["
+
str
(
len
(
s
)
-
1
)
+
":0] "
n
+=
ns
.
get_
name
(
s
)
n
+=
_print
name
(
ns
,
s
)
return
n
return
n
...
@@ -54,7 +65,7 @@ def _printexpr(ns, node):
...
@@ -54,7 +65,7 @@ def _printexpr(ns, node):
if
isinstance
(
node
,
Constant
):
if
isinstance
(
node
,
Constant
):
return
_printconstant
(
node
)
return
_printconstant
(
node
)
elif
isinstance
(
node
,
Signal
):
elif
isinstance
(
node
,
Signal
):
return
ns
.
get_
name
(
node
),
node
.
signed
return
_print
name
(
ns
,
node
),
node
.
signed
elif
isinstance
(
node
,
_Operator
):
elif
isinstance
(
node
,
_Operator
):
arity
=
len
(
node
.
operands
)
arity
=
len
(
node
.
operands
)
r1
,
s1
=
_printexpr
(
ns
,
node
.
operands
[
0
])
r1
,
s1
=
_printexpr
(
ns
,
node
.
operands
[
0
])
...
@@ -246,7 +257,7 @@ def _printcomb(f, ns,
...
@@ -246,7 +257,7 @@ def _printcomb(f, ns,
r
+=
explanation
r
+=
explanation
r
+=
syn_off
r
+=
syn_off
r
+=
"reg "
+
_printsig
(
ns
,
dummy_s
)
+
";
\n
"
r
+=
"reg "
+
_printsig
(
ns
,
dummy_s
)
+
";
\n
"
r
+=
"initial "
+
ns
.
get_
name
(
dummy_s
)
+
" <= 1'd0;
\n
"
r
+=
"initial "
+
_print
name
(
ns
,
dummy_s
)
+
" <= 1'd0;
\n
"
r
+=
syn_on
r
+=
syn_on
r
+=
"
\n
"
r
+=
"
\n
"
...
@@ -267,15 +278,15 @@ def _printcomb(f, ns,
...
@@ -267,15 +278,15 @@ def _printcomb(f, ns,
r
+=
"
\t
$display(
\"
Running comb block #"
+
str
(
n
)
+
"
\"
);
\n
"
r
+=
"
\t
$display(
\"
Running comb block #"
+
str
(
n
)
+
"
\"
);
\n
"
if
blocking_assign
:
if
blocking_assign
:
for
t
in
g
[
0
]:
for
t
in
g
[
0
]:
r
+=
"
\t
"
+
ns
.
get_
name
(
t
)
+
" = "
+
_printexpr
(
ns
,
t
.
reset
)[
0
]
+
";
\n
"
r
+=
"
\t
"
+
_print
name
(
ns
,
t
)
+
" = "
+
_printexpr
(
ns
,
t
.
reset
)[
0
]
+
";
\n
"
r
+=
_printnode
(
ns
,
_AT_BLOCKING
,
1
,
g
[
1
])
r
+=
_printnode
(
ns
,
_AT_BLOCKING
,
1
,
g
[
1
])
else
:
else
:
for
t
in
g
[
0
]:
for
t
in
g
[
0
]:
r
+=
"
\t
"
+
ns
.
get_
name
(
t
)
+
" <= "
+
_printexpr
(
ns
,
t
.
reset
)[
0
]
+
";
\n
"
r
+=
"
\t
"
+
_print
name
(
ns
,
t
)
+
" <= "
+
_printexpr
(
ns
,
t
.
reset
)[
0
]
+
";
\n
"
r
+=
_printnode
(
ns
,
_AT_NONBLOCKING
,
1
,
g
[
1
])
r
+=
_printnode
(
ns
,
_AT_NONBLOCKING
,
1
,
g
[
1
])
if
dummy_signal
:
if
dummy_signal
:
r
+=
syn_off
r
+=
syn_off
r
+=
"
\t
"
+
ns
.
get_
name
(
dummy_d
)
+
" <= "
+
ns
.
get_
name
(
dummy_s
)
+
";
\n
"
r
+=
"
\t
"
+
_print
name
(
ns
,
dummy_d
)
+
" <= "
+
_print
name
(
ns
,
dummy_s
)
+
";
\n
"
r
+=
syn_on
r
+=
syn_on
r
+=
"end
\n
"
r
+=
"end
\n
"
r
+=
"
\n
"
r
+=
"
\n
"
...
@@ -285,7 +296,7 @@ def _printcomb(f, ns,
...
@@ -285,7 +296,7 @@ def _printcomb(f, ns,
def
_printsync
(
f
,
ns
):
def
_printsync
(
f
,
ns
):
r
=
""
r
=
""
for
k
,
v
in
sorted
(
f
.
sync
.
items
(),
key
=
itemgetter
(
0
)):
for
k
,
v
in
sorted
(
f
.
sync
.
items
(),
key
=
itemgetter
(
0
)):
r
+=
"always @(posedge "
+
ns
.
get_
name
(
f
.
clock_domains
[
k
].
clk
)
+
") begin
\n
"
r
+=
"always @(posedge "
+
_print
name
(
ns
,
f
.
clock_domains
[
k
].
clk
)
+
") begin
\n
"
r
+=
_printnode
(
ns
,
_AT_SIGNAL
,
1
,
v
)
r
+=
_printnode
(
ns
,
_AT_SIGNAL
,
1
,
v
)
r
+=
"end
\n\n
"
r
+=
"end
\n\n
"
return
r
return
r
...
...
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