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Kestrel Collaboration
Kestrel LiteX
migen
Commits
94c5fba0
Commit
94c5fba0
authored
12 years ago
by
Sebastien Bourdeauducq
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corelogic: fix signal exports
parent
4f4d809a
Changes
2
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2 changed files
with
8 additions
and
8 deletions
+8
-8
migen/corelogic/divider.py
migen/corelogic/divider.py
+6
-6
migen/corelogic/roundrobin.py
migen/corelogic/roundrobin.py
+2
-2
No files found.
migen/corelogic/divider.py
View file @
94c5fba0
...
...
@@ -4,12 +4,12 @@ class Inst:
def
__init__
(
self
,
w
):
self
.
w
=
w
start_i
=
Signal
()
dividend_i
=
Signal
(
BV
(
w
))
divisor_i
=
Signal
(
BV
(
w
))
ready_o
=
Signal
()
quotient_o
=
Signal
(
BV
(
w
))
remainder_o
=
Signal
(
BV
(
w
))
self
.
start_i
=
Signal
()
self
.
dividend_i
=
Signal
(
BV
(
w
))
self
.
divisor_i
=
Signal
(
BV
(
w
))
self
.
ready_o
=
Signal
()
self
.
quotient_o
=
Signal
(
BV
(
w
))
self
.
remainder_o
=
Signal
(
BV
(
w
))
def
get_fragment
(
self
):
w
=
self
.
w
...
...
This diff is collapsed.
Click to expand it.
migen/corelogic/roundrobin.py
View file @
94c5fba0
...
...
@@ -4,8 +4,8 @@ class Inst:
def
__init__
(
self
,
n
):
self
.
n
=
n
self
.
bn
=
bits_for
(
self
.
n
-
1
)
request
=
Signal
(
BV
(
self
.
n
))
grant
=
Signal
(
BV
(
self
.
bn
))
self
.
request
=
Signal
(
BV
(
self
.
n
))
self
.
grant
=
Signal
(
BV
(
self
.
bn
))
def
get_fragment
(
self
):
cases
=
[]
...
...
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