Commit 70939393 authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
Browse files

corelogic/roundrobin: fix request width (again)

parent 31c722f9
...@@ -5,7 +5,7 @@ from migen.fhdl.structure import * ...@@ -5,7 +5,7 @@ from migen.fhdl.structure import *
class RoundRobin: class RoundRobin:
def __init__(self, n, switch_policy=SP_WITHDRAW): def __init__(self, n, switch_policy=SP_WITHDRAW):
self.n = n self.n = n
self.request = Signal(nbits=self.n) self.request = Signal(self.n)
self.grant = Signal(max=self.n) self.grant = Signal(max=self.n)
self.switch_policy = switch_policy self.switch_policy = switch_policy
if self.switch_policy == SP_CE: if self.switch_policy == SP_CE:
......
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