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Kestrel Collaboration
Kestrel LiteX
migen
Commits
458cfc86
Commit
458cfc86
authored
12 years ago
by
Sebastien Bourdeauducq
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Plain Diff
CSR bus definitions
parent
5acf2e16
Changes
3
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Showing
3 changed files
with
35 additions
and
50 deletions
+35
-50
migen/bus/__init__.py
migen/bus/__init__.py
+0
-0
migen/bus/csr.py
migen/bus/csr.py
+35
-0
test.py
test.py
+0
-50
No files found.
migen/bus/__init__.py
0 → 100644
View file @
458cfc86
This diff is collapsed.
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migen/bus/csr.py
0 → 100644
View file @
458cfc86
from
migen.fhdl
import
structure
as
f
from
functools
import
partial
class
Master
:
def
__init__
(
self
):
d
=
partial
(
f
.
Declare
,
self
)
d
(
"a_o"
,
f
.
BV
(
16
))
d
(
"we_o"
)
d
(
"d_o"
,
f
.
BV
(
32
))
d
(
"d_i"
,
f
.
BV
(
32
))
class
Slave
:
def
__init__
(
self
):
d
=
partial
(
f
.
Declare
,
self
)
d
(
"a_i"
,
f
.
BV
(
16
))
d
(
"we_i"
)
d
(
"d_i"
,
f
.
BV
(
32
))
d
(
"d_o"
,
f
.
BV
(
32
))
class
Interconnect
:
def
__init__
(
self
,
master
,
slaves
):
self
.
master
=
master
self
.
slaves
=
slaves
def
GetFragment
(
self
):
a
=
f
.
Assign
comb
=
[]
rb
=
f
.
Constant
(
0
,
f
.
BV
(
32
))
for
slave
in
self
.
slaves
:
comb
.
append
(
a
(
slave
.
a_i
,
self
.
master
.
a_o
))
comb
.
append
(
a
(
slave
.
we_i
,
self
.
master
.
we_o
))
comb
.
append
(
a
(
slave
.
d_i
,
self
.
master
.
d_o
))
rb
=
rb
|
slave
.
d_o
comb
.
append
(
a
(
master
.
d_i
,
rb
))
return
f
.
Fragment
(
comb
)
\ No newline at end of file
This diff is collapsed.
Click to expand it.
test.py
deleted
100644 → 0
View file @
5acf2e16
from
migen.fhdl
import
structure
as
f
from
migen.fhdl
import
verilog
from
functools
import
partial
class
Divider
:
def
__init__
(
self
,
w
):
self
.
w
=
w
d
=
partial
(
f
.
Declare
,
self
)
d
(
"start_i"
)
d
(
"dividend_i"
,
f
.
BV
(
w
))
d
(
"divisor_i"
,
f
.
BV
(
w
))
d
(
"ready_o"
)
d
(
"quotient_o"
,
f
.
BV
(
w
))
d
(
"remainder_o"
,
f
.
BV
(
w
))
d
(
"_qr"
,
f
.
BV
(
2
*
w
))
d
(
"_counter"
,
f
.
BV
(
f
.
BitsFor
(
w
)))
d
(
"_divisor_r"
,
f
.
BV
(
w
))
d
(
"_diff"
,
f
.
BV
(
w
+
1
))
def
GetFragment
(
self
):
a
=
f
.
Assign
comb
=
[
a
(
self
.
quotient_o
,
self
.
_qr
[:
self
.
w
]),
a
(
self
.
remainder_o
,
self
.
_qr
[
self
.
w
:]),
a
(
self
.
ready_o
,
self
.
_counter
==
f
.
Constant
(
0
,
self
.
_counter
.
bv
)),
a
(
self
.
_diff
,
self
.
remainder_o
-
self
.
_divisor_r
)
]
sync
=
[
f
.
If
(
self
.
start_i
==
1
,
[
a
(
self
.
_counter
,
self
.
w
),
a
(
self
.
_qr
,
self
.
dividend_i
),
a
(
self
.
_divisor_r
,
self
.
divisor_i
)
],
[
f
.
If
(
self
.
ready_o
==
0
,
[
f
.
If
(
self
.
_diff
[
self
.
w
]
==
1
,
[
a
(
self
.
_qr
,
f
.
Cat
(
0
,
self
.
_qr
[:
2
*
self
.
w
-
1
]))],
[
a
(
self
.
_qr
,
f
.
Cat
(
1
,
self
.
_qr
[:
self
.
w
-
1
],
self
.
_diff
[:
self
.
w
]))]),
a
(
self
.
_counter
,
self
.
_counter
-
f
.
Constant
(
1
,
self
.
_counter
.
bv
)),
])
])
]
return
f
.
Fragment
(
comb
,
sync
)
d
=
Divider
(
32
)
f
=
d
.
GetFragment
()
o
=
verilog
.
Convert
(
f
,
{
d
.
start_i
,
d
.
dividend_i
,
d
.
divisor_i
},
{
d
.
ready_o
,
d
.
quotient_o
,
d
.
remainder_o
})
print
(
o
)
\ No newline at end of file
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