Commit 3201554f authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
Browse files

fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()

parent 314a6c77
...@@ -279,11 +279,13 @@ def _printinit(f, ios, ns): ...@@ -279,11 +279,13 @@ def _printinit(f, ios, ns):
r += "end\n\n" r += "end\n\n"
return r return r
def convert(f, ios=set(), name="top", def convert(f, ios=None, name="top",
clock_domains=None, clock_domains=None,
return_ns=False, return_ns=False,
memory_handler=verilog_mem_behavioral.handler, memory_handler=verilog_mem_behavioral.handler,
display_run=False): display_run=False):
if ios is None:
ios = set()
if clock_domains is None: if clock_domains is None:
clock_domains = dict() clock_domains = dict()
for d in f.get_clock_domains(): for d in f.get_clock_domains():
......
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