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Kestrel Collaboration
Kestrel LiteX
migen
Commits
29f7b94e
Commit
29f7b94e
authored
11 years ago
by
Sebastien Bourdeauducq
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bus/wishbone/sram: expose memory component
parent
c5342c5b
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1
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6 additions
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6 deletions
+6
-6
migen/bus/wishbone.py
migen/bus/wishbone.py
+6
-6
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migen/bus/wishbone.py
View file @
29f7b94e
...
@@ -288,20 +288,20 @@ class SRAM(Module):
...
@@ -288,20 +288,20 @@ class SRAM(Module):
bus_data_width
=
flen
(
self
.
bus
.
dat_r
)
bus_data_width
=
flen
(
self
.
bus
.
dat_r
)
if
isinstance
(
mem_or_size
,
Memory
):
if
isinstance
(
mem_or_size
,
Memory
):
assert
(
mem_or_size
.
width
<=
bus_data_width
)
assert
(
mem_or_size
.
width
<=
bus_data_width
)
mem
=
mem_or_size
self
.
mem
=
mem_or_size
else
:
else
:
mem
=
Memory
(
bus_data_width
,
mem_or_size
//
(
bus_data_width
//
8
),
init
=
init
)
self
.
mem
=
Memory
(
bus_data_width
,
mem_or_size
//
(
bus_data_width
//
8
),
init
=
init
)
if
read_only
is
None
:
if
read_only
is
None
:
if
hasattr
(
mem
,
"bus_read_only"
):
if
hasattr
(
self
.
mem
,
"bus_read_only"
):
read_only
=
mem
.
bus_read_only
read_only
=
self
.
mem
.
bus_read_only
else
:
else
:
read_only
=
False
read_only
=
False
###
###
# memory
# memory
port
=
mem
.
get_port
(
write_capable
=
not
read_only
,
we_granularity
=
8
)
port
=
self
.
mem
.
get_port
(
write_capable
=
not
read_only
,
we_granularity
=
8
)
self
.
specials
+=
mem
,
port
self
.
specials
+=
self
.
mem
,
port
# generate write enable signal
# generate write enable signal
if
not
read_only
:
if
not
read_only
:
self
.
comb
+=
[
port
.
we
[
i
].
eq
(
self
.
bus
.
cyc
&
self
.
bus
.
stb
&
self
.
bus
.
we
&
self
.
bus
.
sel
[
i
])
self
.
comb
+=
[
port
.
we
[
i
].
eq
(
self
.
bus
.
cyc
&
self
.
bus
.
stb
&
self
.
bus
.
we
&
self
.
bus
.
sel
[
i
])
...
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