Commit 20a8dd31 authored by whitequark's avatar whitequark
Browse files

doc: explain how to get a VCD dump from simulator.

parent ddd18d23
...@@ -10,7 +10,10 @@ Migen lets you write testbenches using Python's generator functions. Such testbe ...@@ -10,7 +10,10 @@ Migen lets you write testbenches using Python's generator functions. Such testbe
#. Clocking: simulation can be advanced by one clock cycle using ``yield``; #. Clocking: simulation can be advanced by one clock cycle using ``yield``;
#. Composition: control can be transferred to another testbench function using ``yield from run_other()``. #. Composition: control can be transferred to another testbench function using ``yield from run_other()``.
A testbench can be run using the ``run_simulation`` function from ``migen.sim``; ``run_simulation(mod, bench)`` runs the generator function ``bench`` against the logic defined in an FHDL module ``mod``. A testbench can be run using the ``run_simulation`` function from ``migen.sim``; ``run_simulation(dut, bench)`` runs the generator function ``bench`` against the logic defined in an FHDL module ``dut``.
Passing the ``vcd_name="file.vcd"`` argument to ``run_simulation`` will cause it to write a VCD
dump of the signals inside ``dut`` to ``file.vcd``.
Examples Examples
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