- 25 Jul, 2020 1 commit
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Florent Kermarrec authored
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- 24 Jul, 2020 7 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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enjoy-digital authored
Enable use of HalfRateGENSDRPHY on de10nano
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- 23 Jul, 2020 4 commits
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Florent Kermarrec authored
This uses a pre-generated .xci hosted on github, still need to figure out where the best location for it.
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rob-ng15 authored
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rob-ng15 authored
Add Misc("") arguments to various inputs/outputs for stability. Allows de10nano to use HalfRateGENSDRPHY for sdram
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Florent Kermarrec authored
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- 22 Jul, 2020 2 commits
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Florent Kermarrec authored
platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope). Also use pmod connector names in i2s_pmod and sdcard_pmod.
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Florent Kermarrec authored
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- 21 Jul, 2020 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 18 Jul, 2020 1 commit
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Florent Kermarrec authored
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- 17 Jul, 2020 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 15 Jul, 2020 1 commit
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enjoy-digital authored
targets/minispartan6: add support for HalfRateGENSDRPHY
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- 14 Jul, 2020 2 commits
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enjoy-digital authored
Add missing pins to platforms/kc705.py: LPC DP0_M2C/C2M diff pair
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Jędrzej Boczar authored
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- 13 Jul, 2020 1 commit
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Vamsi K Vytla authored
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- 09 Jul, 2020 2 commits
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enjoy-digital authored
OrangeCrab: Update platform
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Greg Davill authored
- fix standard io extensions - Use newly assigned code for orangecrab 1209:5af0
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- 07 Jul, 2020 2 commits
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enjoy-digital authored
arty: Add configuration of I2S pins
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Pawel Sagan authored
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- 06 Jul, 2020 2 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 03 Jul, 2020 1 commit
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Florent Kermarrec authored
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- 01 Jul, 2020 1 commit
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Florent Kermarrec authored
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- 30 Jun, 2020 5 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
DNA/XADC/ICAP are demonstrated in LitePCIe repository and should probably be added with a add_xy method.
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Florent Kermarrec authored
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- 29 Jun, 2020 2 commits
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Florent Kermarrec authored
targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset.
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enjoy-digital authored
Add Logicbone ECP5 board
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- 27 Jun, 2020 1 commit
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Owen Kirby authored
The Logicbone is an Open Source development board for the Lattice ECP5 being developed at https://github.com/oskirby/logicbone
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- 25 Jun, 2020 1 commit
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Florent Kermarrec authored
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