Enable use of HalfRateGENSDRPHY on de10nano

This uses a pre-generated .xci hosted on github, still need to figure out where the best location for it.

Add Misc("") arguments to various inputs/outputs for stability. Allows de10nano to use HalfRateGENSDRPHY for sdram

platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope).

Also use pmod connector names in i2s_pmod and sdcard_pmod.

targets/minispartan6: add support for HalfRateGENSDRPHY

Add missing pins to platforms/kc705.py: LPC DP0_M2C/C2M diff pair

OrangeCrab: Update platform

 - fix standard io extensions
 - Use newly assigned code for orangecrab 1209:5af0

arty: Add configuration of I2S pins

DNA/XADC/ICAP are demonstrated in LitePCIe repository and should probably be added with
a add_xy method.

targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset.

Add Logicbone ECP5 board

The Logicbone is an Open Source development board for the Lattice ECP5
being developed at https://github.com/oskirby/logicbone