target/arty: add eth_ip_configurable switch

fix vc707 default_clk_period

targets/sds1104xe/BaseSoC: Enable Etherbone by default also defaults to Crossover UART when kwargs is empty.

sockit: Add an option to plug in an UART via the GPIO daughter board, make connector pin numbers one-based

platforms/sds1104xe: fix ddram IOStandard (SSTL15, thanks @tmbinc) and add INTERNAL_VREF on ddram banks.

platform/de10nano: fix programmer (thanks @Godtec, see https://github.com/enjoy-digital/litex/pull/811).

vc707.py: clk156 add missing constraint

arrow_sockit: add support for MiSTer XS SDRAM modules

nexys_video: enable symbiflow toolchain

Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>

targets/colorlight_i5: use .bit stream instead of .svf when loading.

Be friendlier about incompatible options.

./tec0117.py --build --load

Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Feb  1 2021 13:09:35
 BIOS CRC passed (5abceb2e)

 Migen git sha1: 40b1092
 LiteX git sha1: f324f953

--=============== SoC ==================--
CPU:		VexRiscv_Lite @ 25MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		24KiB
SRAM:		4KiB
L2:		0KiB
SDRAM:		8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
  Write: 0x40000000-0x40200000 2MiB
   Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
  Write speed: 5MiB/s
   Read speed: 6MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> mem_list

Available memory regions:
ROM       0x00000000 0x6000
SRAM      0x01000000 0x1000
SPIFLASH  0x80000000 0x1000000
MAIN_RAM  0x40000000 0x800000
CSR       0x82000000 0x10000

litex> mem_test 0x40000000 0x800000

Memtest at 0x40000000 (8MiB)...
  Write: 0x40000000-0x40800000 8MiB
   Read: 0x40000000-0x40800000 8MiB
Memtest OK

litex>

tec0117: disable BIOS XIP from SPI Flash for now since not working (SPÏ Flash set to power down mode with bitstream?).

sockit: Fix cable name, default to jtag_atlantic

Support file for the ZTEX USB-FPGA Module 2.13

Add flash to SPI flash support for board ECPIX5

Add flash to SPI flash support for board ECPIX5 (needs update to openfpgaloader.py from litex to work)

Merge upstream before changes

Collect --with-ethernet/--with-etherbone, --with-spi-sdcard/--with-sdcard,
etc. into ArgumentParser.add_mutually_exclusive_group()s.  That way, we
get pretty --help output, and appropriate error messages if somebody
tries to ask for something that doesn't make sense.

Still a WIP but able to do the P&R with modifications on LiteX to generate
the IO_PORT constraints but not the IO_LOC for the SDRAM pins.

ECPIX-5: ddram: Add missing address pin.

Fixes #161

rst_n is optional in LiteEth's PHYs.